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1. 发明申请

US20080169839A1 STRUCTURE FOR A CURRENT CONTROL MECHANISM FOR DYNAMIC LOGIC KEEPER CIRCUITS 失效
标题翻译：用于动态逻辑保护电路的电流控制机构的结构
公开(公告)号：US20080169839A1
公开(公告)日：2008-07-17
申请号：US11851133
申请日：2007-09-06
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/0175
CPC分类号： H03K19/0963
摘要： A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种用于集成电路的设计结构，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

2. 发明申请

US20080169837A1 Current Control Mechanism For Dynamic Logic Keeper Circuits In An Integrated Circuit And Method Of Regulating Same 有权
标题翻译：一种集成电路中动态逻辑控制器电路的电流控制机制及其调节方法
公开(公告)号：US20080169837A1
公开(公告)日：2008-07-17
申请号：US11623112
申请日：2007-01-15
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/0175
CPC分类号： H03K19/0963
摘要： An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种集成电路，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

3. 发明授权

US07573300B2 Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same 有权
标题翻译：集成电路中动态逻辑门控电路的电流控制机制及其调节方法
公开(公告)号：US07573300B2
公开(公告)日：2009-08-11
申请号：US11623112
申请日：2007-01-15
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种集成电路，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

4. 发明授权

US07471114B2 Design structure for a current control mechanism for power networks and dynamic logic keeper circuits 失效
标题翻译：用于电力网络和动态逻辑门控电路的电流控制机构的设计结构
公开(公告)号：US07471114B2
公开(公告)日：2008-12-30
申请号：US11851133
申请日：2007-09-06
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种用于集成电路的设计结构，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

5. 发明授权

US07548080B2 Method and apparatus for burn-in optimization 失效
标题翻译：老化优化的方法和装置
公开(公告)号：US07548080B2
公开(公告)日：2009-06-16
申请号：US11538833
申请日：2006-10-05
申请人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
IPC分类号： G01R31/02
CPC分类号： G01R31/287 , G01R31/2874
摘要： The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.
摘要翻译：本发明提供一种用于优化集成电路的老化的方法和装置。该方法的一个实施例包括：执行集成电路的老化过程的第一部分; 在老化过程的第一部分期间监测集成电路的功耗; 增加老化温度，直到集成电路的功耗达到预定的最大功耗; 以及在增加的老化温度下执行集成电路的老化过程的后续部分。

6. 发明授权

US07141998B1 Method and apparatus for burn-in optimization 失效
公开(公告)号：US07141998B1
公开(公告)日：2006-11-28
申请号：US10908620
申请日：2005-05-19
申请人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
IPC分类号： G01R31/02
CPC分类号： G01R31/287 , G01R31/2874
摘要： The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.

7. 发明授权

US08839054B2 Read only memory (ROM) with redundancy 有权
标题翻译：只读存储器（ROM）冗余
公开(公告)号：US08839054B2
公开(公告)日：2014-09-16
申请号：US13445187
申请日：2012-04-12
申请人： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
发明人： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G06F11/0793 , G11C17/00 , G11C29/4401 , G11C29/822
摘要： A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.
摘要翻译：提供了具有冗余性和使用方法的只读存储器（ROM）。具有冗余的ROM包括耦合到具有一个或多个冗余修复的修复电路的可编程阵列。一个或多个冗余修复包括字地址匹配逻辑块，数据I / O地址和三态缓冲器。字地址匹配逻辑块作为控制输入提供给三态缓冲器，并且将数据I / O地址作为输入提供给三态缓冲器。提供每个冗余修复的三态缓冲器的输出作为一个或多个逻辑器件的第一输入。提供ROM位单元阵列的一个或多个数据输出作为一个或多个逻辑器件中的相应一个的第二输入。

8. 发明申请

US20090179670A1 PERFORMANCE INVERSION DETECTION CIRCUIT AND A DESIGN STRUCTURE FOR THE SAME 审中-公开
标题翻译：性能反相检测电路及其设计结构
公开(公告)号：US20090179670A1
公开(公告)日：2009-07-16
申请号：US12014430
申请日：2008-01-15
申请人： Albert M. Chu , John A. Fifield , Daryl M. Seitzer , Hongfei Wu
发明人： Albert M. Chu , John A. Fifield , Daryl M. Seitzer , Hongfei Wu
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F2200/447 , H03F2203/45586 , H03F2203/45618 , H03F2203/45622
摘要： A circuit containing a parallel connection of a first sub-circuit and a second sub-circuit is provided. The first sub-circuit comprises a serial connection of a first field effect transistor having a first threshold voltage and a first voltage dividing device. The second sub-circuit comprises a serial connection of a second field effect transistor having a second threshold voltage, which is different from the first threshold voltage, and a second voltage dividing device. The voltage between the first field effect transistor and the first voltage dividing device is compared with the voltage between the second field effect transistor and the second voltage dividing device so that a signal may be generated at a temperature at which the ratio of a performance parameter such as on-current between the first and second field effect transistors crosses over a predefined value. The signal may be advantageously employed to actively control circuit characteristics.
摘要翻译：提供了包含第一子电路和第二子电路的并联连接的电路。第一子电路包括具有第一阈值电压的第一场效应晶体管和第一分压装置的串联连接。第二子电路包括具有与第一阈值电压不同的第二阈值电压的第二场效应晶体管的串联连接和第二分压装置。将第一场效应晶体管和第一分压装置之间的电压与第二场效应晶体管和第二分压装置之间的电压进行比较，使得可以在这样的温度下产生信号，因为第一和第二场效应晶体管之间的导通电流跨越预定值。可以有利地使用该信号来主动地控制电路特性。

9. 发明授权

US08643987B2 Current leakage in RC ESD clamps 有权
标题翻译： RC ESD钳位电流泄漏
公开(公告)号：US08643987B2
公开(公告)日：2014-02-04
申请号：US13464131
申请日：2012-05-04
申请人： Albert M. Chu , Joseph A. Iadanza , Mujahid Muhammad , Daryl M. Seitzer , Rohit Shetty , Jane S. Tu
发明人： Albert M. Chu , Joseph A. Iadanza , Mujahid Muhammad , Daryl M. Seitzer , Rohit Shetty , Jane S. Tu
IPC分类号： H02H9/00 , H02H3/20 , H02H9/04 , H02H3/22
CPC分类号： H02H9/046
摘要： Aspects of the invention provide an electrostatic discharge (ESD) protection device for eliminating current leakage, and a related method. In one embodiment, an ESD protection device includes: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply for the trigger circuit, such that the trigger circuit generates a trigger pulse, in response to selecting the negative bias voltage supply, to turn off the ESD clamp during normal operation.
摘要翻译：本发明提供一种用于消除电流泄漏的静电放电（ESD）保护装置及相关方法。在一个实施例中，ESD保护装置包括：用于接收电源电压的电阻器 - 电容器（RC）电路; 包括用于在ESD事件期间保护IC的多个n型场效应晶体管（nFET）的ESD钳位; 触发电路，用于接收RC电路的输出并产生触发脉冲以在ESD事件期间导通ESD钳位; 以及连接到触发电路的nFET偏置选择电路，nFET偏置选择电路，用于选择触发电路的低电压电源或负偏置电压源，使得触发电路响应于触发电路产生触发脉冲选择负偏压电源，在正常工作期间关闭ESD钳位。

10. 发明申请

US20130293991A1 CURRENT LEAKAGE IN RC ESD CLAMPS 有权
标题翻译： RC ESD CLAMP中的电流泄漏
公开(公告)号：US20130293991A1
公开(公告)日：2013-11-07
申请号：US13464131
申请日：2012-05-04
申请人： Albert M. Chu , Joseph A. Iadanza , Mujahid Muhammad , Daryl M. Seitzer , Rohit Shetty , Jane S. Tu
发明人： Albert M. Chu , Joseph A. Iadanza , Mujahid Muhammad , Daryl M. Seitzer , Rohit Shetty , Jane S. Tu
IPC分类号： H02H9/04 , H01L27/06
CPC分类号： H02H9/046
摘要： Aspects of the invention provide an electrostatic discharge (ESD) protection device for eliminating current leakage, and a related method. In one embodiment, an ESD protection device includes: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply for the trigger circuit, such that the trigger circuit generates a trigger pulse, in response to selecting the negative bias voltage supply, to turn off the ESD clamp during normal operation.
摘要翻译：本发明提供一种用于消除电流泄漏的静电放电（ESD）保护装置及相关方法。在一个实施例中，ESD保护装置包括：用于接收电源电压的电阻器 - 电容器（RC）电路; 包括用于在ESD事件期间保护IC的多个n型场效应晶体管（nFET）的ESD钳位; 触发电路，用于接收RC电路的输出并产生触发脉冲以在ESD事件期间导通ESD钳位; 以及连接到触发电路的nFET偏置选择电路，nFET偏置选择电路，用于选择触发电路的低电压电源或负偏置电压源，使得触发电路响应于触发电路产生触发脉冲选择负偏压电源，在正常工作期间关闭ESD钳位。

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