专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08299500B2 Silicon germanium heterojunction bipolar transistor having interstitial trapping layer in base region 有权
标题翻译：硅锗异质结双极晶体管在基极区域具有间隙捕获层
公开(公告)号：US08299500B2
公开(公告)日：2012-10-30
申请号：US11161936
申请日：2005-08-23
申请人： Wade J. Hodge , Alvin J. Joseph , Rajendran Krishnasamy , Qizhi Liu , Bradley A. Orner
发明人： Wade J. Hodge , Alvin J. Joseph , Rajendran Krishnasamy , Qizhi Liu , Bradley A. Orner
IPC分类号： H01L29/737
CPC分类号： H01L29/7378 , H01L21/8249 , H01L29/1004
摘要： A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
摘要翻译：异质结双极晶体管（HBT），包括至少一个HBT的集成电路（IC）芯片和形成IC的方法。 HBT包括具有一个或多个掩埋间隙屏障层的外在基底。外部基极可以用硼重掺杂，并且每个掩埋的间隙势垒层掺杂含有碳的掺杂剂，例如碳或SiGe：C。外基的表面可以被硅化。

2. 发明授权

US08853043B2 Silicon germanium (SiGe) heterojunction bipolar transistor (HBT) 有权
标题翻译：硅锗（SiGe）异质结双极晶体管（HBT）
公开(公告)号：US08853043B2
公开(公告)日：2014-10-07
申请号：US13610641
申请日：2012-09-11
申请人： Wade J. Hodge , Alvin J. Joseph , Rajendran Krishnasamy , Qizhi Liu , Bradley A. Orner
发明人： Wade J. Hodge , Alvin J. Joseph , Rajendran Krishnasamy , Qizhi Liu , Bradley A. Orner
IPC分类号： H01L21/331 , H01L21/8222 , H01L29/737 , H01L29/10 , H01L21/8249
CPC分类号： H01L29/7378 , H01L21/8249 , H01L29/1004
摘要： A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
摘要翻译：异质结双极晶体管（HBT），包括至少一个HBT的集成电路（IC）芯片和形成IC的方法。 HBT包括具有一个或多个掩埋间隙屏障层的外在基底。外部基极可以用硼重掺杂，并且每个掩埋的间隙势垒层掺杂含有碳的掺杂剂，例如碳或SiGe：C。外基的表面可以被硅化。

3. 发明申请

US20130005108A1 SILICON GERMANIUM (SiGe) HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) 有权
标题翻译：硅锗（SiGe）异相双极晶体管（HBT）
公开(公告)号：US20130005108A1
公开(公告)日：2013-01-03
申请号：US13610641
申请日：2012-09-11
申请人： Wade J. Hodge , Alvin J. Joseph , Rajendran Krishnasamy , Qizhi Liu , Bradley A. Orner
发明人： Wade J. Hodge , Alvin J. Joseph , Rajendran Krishnasamy , Qizhi Liu , Bradley A. Orner
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L21/8249 , H01L29/1004
摘要： A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
摘要翻译：异质结双极晶体管（HBT），包括至少一个HBT的集成电路（IC）芯片和形成IC的方法。 HBT包括具有一个或多个掩埋间隙屏障层的外在基底。外部基极可以用硼重掺杂，并且每个掩埋的间隙势垒层掺杂含有碳的掺杂剂，例如碳或SiGe：C。外基的表面可以被硅化。

4. 发明授权

US07625792B2 Method of base formation in a BiCMOS process 有权
标题翻译： BiCMOS工艺中碱形成的方法
公开(公告)号：US07625792B2
公开(公告)日：2009-12-01
申请号：US10599938
申请日：2005-04-06
申请人： Peter J. Geiss , Alvin J. Joseph , Qizhi Liu , Bradley A. Orner
发明人： Peter J. Geiss , Alvin J. Joseph , Qizhi Liu , Bradley A. Orner
IPC分类号： H01L21/8238
CPC分类号： H01L29/0804 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/66287
摘要： Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinsic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.
摘要翻译：公开了一种双极互补金属氧化物半导体（BiCMOS）或NPN / PNP器件，其具有集电极，集电极之上的本征基极，与集电极相邻的浅沟槽隔离区，在本征基极之上的凸起的外部基极，T形发射极在外部基极之上，邻近发射极的间隔物和通过间隔物与发射极分离的硅化物层。

5. 发明授权

US06911681B1 Method of base formation in a BiCMOS process 有权
标题翻译： BiCMOS工艺中碱形成的方法
公开(公告)号：US06911681B1
公开(公告)日：2005-06-28
申请号：US10709113
申请日：2004-04-14
申请人： Peter J. Geiss , Alvin J. Joseph , Qizhi Liu , Bradley A. Orner
发明人： Peter J. Geiss , Alvin J. Joseph , Qizhi Liu , Bradley A. Orner
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/10 , H01L29/739
CPC分类号： H01L29/0804 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/66287
摘要： Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.
摘要翻译：公开了一种双极互补金属氧化物半导体（BiCMOS）或NPN / PNP器件，其具有集电极，集电极之上的本征基极，与集电极相邻的浅沟槽隔离区，在本征基极之上的凸起的外部基极，T形发射极在离子基底之上，邻近发射极的间隔物，以及通过间隔物与发射极分离的硅化物层。

6. 发明申请

US20090039522A1 BIPOLAR AND CMOS INTEGRATION WITH REDUCED CONTACT HEIGHT 失效
标题翻译：双极和CMOS集成与降低接触高度
公开(公告)号：US20090039522A1
公开(公告)日：2009-02-12
申请号：US10596573
申请日：2003-12-16
申请人： Zhong-Xiang He , Bradley A. Orner , Vidhya Ramachandran , Alvin J. Joseph , Stephen A. St. Onge , Ping-Chuan Wang
发明人： Zhong-Xiang He , Bradley A. Orner , Vidhya Ramachandran , Alvin J. Joseph , Stephen A. St. Onge , Ping-Chuan Wang
IPC分类号： H01L23/52
CPC分类号： H01L21/76838 , H01L21/76802 , H01L21/8249 , H01L23/485 , H01L23/5389 , H01L27/0623 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.
摘要翻译：公开了一种集成电路结构的方法和结构，其包括多个互补金属氧化物半导体（CMOS）晶体管和位于单个衬底上的多个垂直双极晶体管。垂直双极晶体管比CMOS晶体管更高的器件。在该结构中，钝化层位于衬底上方，并且位于垂直双极晶体管和CMOS晶体管之间。布线层位于钝化层的上方。垂直双极晶体管与布线层直接接触，并且CMOS晶体管通过延伸穿过钝化层的触点连接到布线层。

7. 发明授权

US07701015B2 Bipolar and CMOS integration with reduced contact height 失效
标题翻译：双极和CMOS集成，降低接触高度
公开(公告)号：US07701015B2
公开(公告)日：2010-04-20
申请号：US10596573
申请日：2003-12-16
申请人： Zhong-Xiang He , Bradley A. Orner , Vidhya Ramachandran , Alvin J. Joseph , Stephen A. St. Onge , Ping-Chuan Wang
发明人： Zhong-Xiang He , Bradley A. Orner , Vidhya Ramachandran , Alvin J. Joseph , Stephen A. St. Onge , Ping-Chuan Wang
IPC分类号： H01L29/72
CPC分类号： H01L21/76838 , H01L21/76802 , H01L21/8249 , H01L23/485 , H01L23/5389 , H01L27/0623 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.
摘要翻译：公开了一种集成电路结构的方法和结构，其包括多个互补金属氧化物半导体（CMOS）晶体管和位于单个衬底上的多个垂直双极晶体管。垂直双极晶体管比CMOS晶体管更高的器件。在该结构中，钝化层位于衬底上方，并且位于垂直双极晶体管和CMOS晶体管之间。布线层位于钝化层的上方。垂直双极晶体管与布线层直接接触，并且CMOS晶体管通过延伸穿过钝化层的触点连接到布线层。

8. 发明授权

US08236662B2 Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration 有权
标题翻译：双极晶体管具有凸起的外部自对准基极，使用BiCMOS集成的选择性外延生长
公开(公告)号：US08236662B2
公开(公告)日：2012-08-07
申请号：US12949108
申请日：2010-11-18
申请人： Natalie B. Feilchenfeld , Bradley A. Orner , Benjamin T. Voegeli
发明人： Natalie B. Feilchenfeld , Bradley A. Orner , Benjamin T. Voegeli
IPC分类号： H01L21/8249
CPC分类号： H01L29/7302 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/66287
摘要： High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.
摘要翻译：具有凸起的外部自对准基极的高性能双极晶体管集成到包含CMOS器件的BiCMOS结构中。通过形成焊盘层并相对于先前存在的CMOS器件的源极和漏极提高本征基极层的高度，并且通过选择性外延形成外部基极，在外部基极的光刻图案化期间，拓扑变化的影响被最小化。而且，通过在双极结构的制造期间不采用任何化学机械平面化工艺，工艺集成的复杂性降低。可以形成内部间隔物或外部隔离物以将基底与发射器隔离。垫层，本征基层和非本征基层形成具有重合的外侧壁表面的台面结构。

9. 发明授权

US07691734B2 Deep trench based far subcollector reachthrough 失效
标题翻译：深沟渠远极子集线器达到
公开(公告)号：US07691734B2
公开(公告)日：2010-04-06
申请号：US11680637
申请日：2007-03-01
申请人： Bradley A. Orner , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
发明人： Bradley A. Orner , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
IPC分类号： H01L21/04
CPC分类号： H01L21/763 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
摘要翻译：通过将掺杂剂离子注入到初始半导体衬底的区域中，随后半导体材料的外延生长，形成位于超过常规离子注入范围的深度的远的子集电极或掩埋掺杂半导体层。通过从沉积在邻接远子集电极的至少一个深沟槽中的掺杂材料层向外扩散掺杂剂形成远子集电极的到达区域。穿通区域可形成为围绕至少一个深沟槽或仅在至少一个深沟槽的一侧上。如果至少一个沟槽的内部电连接到通孔区域，则可以在至少一个沟槽内的掺杂填充材料上形成金属接触。如果不是，则在与接触区域接触的次级通过区域上形成金属接触。

10. 发明申请

US20080211064A1 DEEP TRENCH BASED FAR SUBCOLLECTOR REACHTHROUGH 失效
标题翻译：深度基础的FAR SUBCOLLECTOR REACHTHROUGH
公开(公告)号：US20080211064A1
公开(公告)日：2008-09-04
申请号：US11680637
申请日：2007-03-01
申请人： Bradley A. Orner , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
发明人： Bradley A. Orner , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
IPC分类号： H01L29/06 , H01L21/425
CPC分类号： H01L21/763 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
摘要翻译：通过将掺杂剂离子注入到初始半导体衬底的区域中，随后半导体材料的外延生长，形成位于超过常规离子注入范围的深度的远的子集电极或掩埋掺杂半导体层。通过从沉积在邻接远子集电极的至少一个深沟槽中的掺杂材料层向外扩散掺杂剂形成远子集电极的到达区域。穿通区可以形成在至少一个深沟槽周围，或仅在至少一个深沟槽的一侧上。如果至少一个沟槽的内部电连接到通孔区域，则可以在至少一个沟槽内的掺杂填充材料上形成金属接触。如果不是，则在与接触区域接触的次级通过区域上形成金属接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式