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1. 发明申请

US20130080748A1 MULTI-PROCESSOR DATA PROCESSING SYSTEM HAVING SYNCHRONIZED EXIT FROM DEBUG MODE AND METHOD THEREFOR 有权
标题翻译：具有从调试模式同步退出的多处理器数据处理系统及其方法
公开(公告)号：US20130080748A1
公开(公告)日：2013-03-28
申请号：US13239649
申请日：2011-09-22
申请人： WILLIAM C. MOYER , Jimmy Gumulja , Gary L. Miller
发明人： WILLIAM C. MOYER , Jimmy Gumulja , Gary L. Miller
IPC分类号： G06F9/44 , G06F9/30
CPC分类号： G06F11/3656 , G06F9/30076
摘要： A data processing system includes a plurality of data processors, debug logic, and linking logic. The debug logic is coupled to each data processor of the plurality of data processors, and is for providing an instruction for exiting debug mode to the plurality of data processors. The linking logic is coupled to the debug logic and to each of the plurality of data processors. The linking logic is for linking selected ones of the plurality of data processors with each other and to the debug logic. The debug logic provides the instruction for exiting the debug mode when the selected ones of the plurality of data processors are linked in parallel by the linking logic.
摘要翻译：数据处理系统包括多个数据处理器，调试逻辑和链接逻辑。调试逻辑耦合到多个数据处理器中的每个数据处理器，并且用于提供用于将调试模式退出到多个数据处理器的指令。链接逻辑耦合到调试逻辑和多个数据处理器中的每一个。链接逻辑用于将多个数据处理器中的选定的数据处理器彼此链接到调试逻辑。当所述多个数据处理器中的所选择的数据处理器被所述链接逻辑并行链接时，所述调试逻辑提供用于退出所述调试模式的指令。

2. 发明授权

US08700955B2 Multi-processor data processing system having synchronized exit from debug mode and method therefor 有权
标题翻译：具有从调试模式同步退出的多处理器数据处理系统及其方法
公开(公告)号：US08700955B2
公开(公告)日：2014-04-15
申请号：US13239649
申请日：2011-09-22
申请人： William C. Moyer , Jimmy Gumulja , Gary L. Miller
发明人： William C. Moyer , Jimmy Gumulja , Gary L. Miller
IPC分类号： G06F11/00
CPC分类号： G06F11/3656 , G06F9/30076
摘要： A data processing system includes a plurality of data processors, debug logic, and linking logic. The debug logic is coupled to each data processor of the plurality of data processors, and is for providing an instruction for exiting debug mode to the plurality of data processors. The linking logic is coupled to the debug logic and to each of the plurality of data processors. The linking logic is for linking selected ones of the plurality of data processors with each other and to the debug logic. The debug logic provides the instruction for exiting the debug mode when the selected ones of the plurality of data processors are linked in parallel by the linking logic.
摘要翻译：数据处理系统包括多个数据处理器，调试逻辑和链接逻辑。调试逻辑耦合到多个数据处理器中的每个数据处理器，并且用于提供用于将调试模式退出到多个数据处理器的指令。链接逻辑耦合到调试逻辑和多个数据处理器中的每一个。链接逻辑用于将多个数据处理器中的选定的数据处理器彼此链接到调试逻辑。当所述多个数据处理器中的所选择的数据处理器被所述链接逻辑并行链接时，所述调试逻辑提供用于退出所述调试模式的指令。

3. 发明申请

US20090222693A1 METHOD AND APPARATUS FOR MASKING DEBUG RESOURCES 有权
标题翻译：掩蔽调查资源的方法和装置
公开(公告)号：US20090222693A1
公开(公告)日：2009-09-03
申请号：US12040221
申请日：2008-02-29
申请人： William C. Moyer , Alistair P. Robertson , Jimmy Gumulja
发明人： William C. Moyer , Alistair P. Robertson , Jimmy Gumulja
IPC分类号： G06F11/00
CPC分类号： G06F11/3656
摘要： A method uses an integrated circuit having a debug status register. The integrated circuit is for being debugged by a hardware debugger external to the integrated circuit and has a processing unit for executing debug software. The debug status register is coupled to the processing unit and is for being coupled to the hardware debugger. The method includes updating the debug status register with hardware status flags arising from running the hardware debugger and software status flags arising from running the debug software. The method further includes masking locations in the debug status register where the hardware status flags are located from being read by the debug software while allowing the hardware status flags and the software status flags to be read by the hardware debugger. This is particularly useful in using the hardware debugger in debugging the debug software.
摘要翻译：一种方法使用具有调试状态寄存器的集成电路。集成电路由用于由集成电路外部的硬件调试器调试，并具有用于执行调试软件的处理单元。调试状态寄存器耦合到处理单元，并且用于耦合到硬件调试器。该方法包括通过运行硬件调试器和由运行调试软件产生的软件状态标志产生的硬件状态标志来更新调试状态寄存器。该方法还包括在调试状态寄存器中屏蔽硬件状态标志位置的位置，以便由调试软件读取，同时允许硬件调试器读取硬件状态标志和软件状态标志。这在调试调试软件时使用硬件调试器特别有用。

4. 发明申请

US20080126769A1 DATA PROCESSING WITH RECONFIGURABLE REGISTERS 有权
标题翻译：使用可重新配置的寄存器进行数据处理
公开(公告)号：US20080126769A1
公开(公告)日：2008-05-29
申请号：US11460090
申请日：2006-07-26
申请人： William C. Moyer , Jimmy Gumulja
发明人： William C. Moyer , Jimmy Gumulja
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30112 , G06F9/30134 , G06F9/30141
摘要： A data processing system includes functional circuitry which performs at least one data processing function, a register file coupled to the functional circuitry and having a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system, where a portion of the plurality of GPRs are reconfigurable as test registers during a test mode, and control circuitry which provides a test enable indicator to the register file. The portion of the plurality of GPRs, in response to the test enable indicator indicating the test mode is enabled, operates to accumulate test data from predetermined circuit nodes within the functional circuitry. In one aspect, the portion of the plurality of GPRs are reconfigured as multiple input shift registers (MISRs) during the test mode and generate signatures based on the test data.
摘要翻译：数据处理系统包括执行至少一个数据处理功能的功能电路，耦合到功能电路的寄存器文件，并具有多个通用寄存器（GPR），其被作为用于数据处理系统的用户编程模型的一部分，其中在测试模式期间多个GPR的一部分可重新配置为测试寄存器，以及向该寄存器文件提供测试使能指示符的控制电路。响应于指示测试模式的测试使能指示符被使能，多个GPR的部分操作以从功能电路内的预定电路节点累积测试数据。在一个方面，多个GPR的部分在测试模式期间被重新配置为多个输入移位寄存器（MISR），并且基于测试数据生成签名。

5. 发明授权

US07130943B2 Data processing system with bus access retraction 有权
标题翻译：数据处理系统与总线访问回退
公开(公告)号：US07130943B2
公开(公告)日：2006-10-31
申请号：US10954809
申请日：2004-09-30
申请人： William C. Moyer , Jimmy Gumulja , Brett W. Murdock
发明人： William C. Moyer , Jimmy Gumulja , Brett W. Murdock
IPC分类号： G06F13/00 , G06F3/00 , G06F13/36
CPC分类号： G06F13/362
摘要： A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.
摘要翻译：总线主控器可以基于当前挂起的访问的一个或多个特征来选择性地撤回当前未决的访问。以这种方式，总线主控可以更好地控制其访问请求。一个或多个特征可以包括例如访问的类型（例如读/写，指令/数据，突发/非突发等），访问的顺序或顺序，被访问的地址（例如哪个地址范围是访问或正在访问哪个设备），总线主机请求撤回（在例如多主机系统中）或其任何组合。总线仲裁器还可以基于当前待决的访问请求或后续访问请求的一个或多个特征来选择性地撤回当前待决的访问请求，以有利于后续的访问请求。这些特征可以包括上面列出的任何一个，请求主机的优先级（例如请求主机之间的优先级增量），请求主机的其他属性或其任何组合。

6. 发明申请

US20090300249A1 SELECTIVE MISR DATA ACCUMULATION DURING EXCEPTION PROCESSING 失效
标题翻译：在异常处理期间的选择性MISR数据累积
公开(公告)号：US20090300249A1
公开(公告)日：2009-12-03
申请号：US12130012
申请日：2008-05-30
申请人： William C. Moyer , Jimmy Gumulja
发明人： William C. Moyer , Jimmy Gumulja
IPC分类号： G06F13/24
CPC分类号： G06F11/27 , G06F11/2236
摘要： A plurality of test points are located at predetermined circuit nodes in a processing system. Test code which includes a set of software-controllable interrupts is executed using a multiple input shift register (MISR) to generate a MISR signature. One or more selected software-controllable interrupt types are determined. During execution of the test code, the MISR is used to also accumulate data values from the plurality of test points during exception processing of one or more of the software-controllable interrupts within the set of software-controllable interrupts which are of the one or more selected software-controllable interrupt types to generate the MISR signature. A test control register has a plurality of fields, each for selecting or not selecting a corresponding software-controllable interrupt type.
摘要翻译：多个测试点位于处理系统中的预定电路节点处。使用多输入移位寄存器（MISR）执行包括一组软件可控中断的测试代码，以生成MISR签名。确定一个或多个选择的软件可控中断类型。在执行测试代码期间，MISR还用于在异常处理期间累积来自多个测试点的数据值，该异常处理中的软件可控中断集合中的一个或多个软件可控中断是一个或多个选择软件可控中断类型来生成MISR签名。测试控制寄存器具有多个场，每个场用于选择或不选择相应的软件可控中断类型。

7. 发明申请

US20090187789A1 METHOD AND APPARATUS FOR HANDLING SHARED HARDWARE AND SOFTWARE DEBUG RESOURCE EVENTS IN A DATA PROCESSING SYSTEM 有权
标题翻译：在数据处理系统中处理共享硬件和软件调试资源事件的方法和装置
公开(公告)号：US20090187789A1
公开(公告)日：2009-07-23
申请号：US12016664
申请日：2008-01-18
申请人： William C. Moyer , Jimmy Gumulja , Jeffrey W. Scott
发明人： William C. Moyer , Jimmy Gumulja , Jeffrey W. Scott
IPC分类号： G06F11/00
CPC分类号： G06F11/3656
摘要： For some data processing systems, it is important to be able to handle overlapping debug events generated by a shared set of debug resources which are trying to cause both exception processing and debug mode entry. However, exception processing and debug mode entry generally have conflicting requirements. In one embodiment, exception priority processing is initially given to the software debug event. Normal state saving is performed and the first instruction of the debug exception handler is fetched, but not executed. Priority is then switched from the software debug event to the hardware debug event and a debug halted state is entered. Once processing of the hardware debug event has been completed, priority is returned to the software debug event and the debug exception handler is executed.
摘要翻译：对于一些数据处理系统，重要的是能够处理由共同的一组调试资源生成的重叠调试事件，这些调试资源试图引起异常处理和调试模式输入。但是，异常处理和调试模式条目通常具有冲突的要求。在一个实施例中，最初给出软件调试事件的异常优先级处理。执行正常状态保存，并且提取调试异常处理程序的第一条指令，但不执行。优先级然后从软件调试事件切换到硬件调试事件，并且进入调试停止状态。一旦硬件调试事件的处理完成，优先级将返回到软件调试事件，并执行调试异常处理程序。

8. 发明申请

US20100262811A1 DEBUG SIGNALING IN A MULTIPLE PROCESSOR DATA PROCESSING SYSTEM 有权
标题翻译：多处理器数据处理系统中的调试信号
公开(公告)号：US20100262811A1
公开(公告)日：2010-10-14
申请号：US12420521
申请日：2009-04-08
申请人： William C. Moyer , Jimmy Gumulja
发明人： William C. Moyer , Jimmy Gumulja
IPC分类号： G06F9/30 , G06F1/12
CPC分类号： G06F11/1679 , G06F11/1629 , G06F11/1695 , G06F11/3632
摘要： A system includes a first processor, a second processor, a first clock coupled to the first processor, and a third clock coupled to the first processor and to the second processor. The first processor includes debug circuitry coupled to receive the third clock, synchronization circuitry coupled to receive the first clock, wherein the synchronization circuitry receives a first request to enter a debug mode and provides a first synced debug entry request signal and wherein the first synced debug entry request signal is synchronized with respect to the first clock, and an input for receiving a second synced debug entry request signal from the second processor wherein the first processor waits to enter the debug mode until the first synced debug entry request signal and the second synced debug entry request signal are both asserted.
摘要翻译：系统包括第一处理器，第二处理器，耦合到第一处理器的第一时钟以及耦合到第一处理器和第二处理器的第三时钟。第一处理器包括耦合以接收第三时钟的调试电路，耦合以接收第一时钟的同步电路，其中同步电路接收进入调试模式的第一请求并提供第一同步调试输入请求信号，并且其中第一同步调试输入请求信号相对于第一时钟同步，以及用于从第二处理器接收第二同步调试条目请求信号的输入，其中第一处理器等待进入调试模式，直到第一同步调试条目请求信号和第二同步调试进入请求信号都被断言。

9. 发明授权

US07627795B2 Pipelined data processor with deterministic signature generation 有权
标题翻译：具有确定性签名生成的流水线数据处理器
公开(公告)号：US07627795B2
公开(公告)日：2009-12-01
申请号：US11460086
申请日：2006-07-26
申请人： William C. Moyer , Jimmy Gumulja
发明人： William C. Moyer , Jimmy Gumulja
IPC分类号： G01R31/28 , G01R31/26 , G11C29/00
CPC分类号： G01R31/318566 , G01R31/318547 , G11C29/1201
摘要： A pipelined data processing system includes functional circuitry having a plurality of test points located at predetermined circuit nodes within the functional circuitry, at least one staging storage element associated with a pipeline stage of the data processing system which is coupled to receive test data directly from the plurality of test points, and a multiple input shift register (MISR) coupled to receive test data from the at least one staging storage element and provide a MISR result. In one aspect, the at least on staging storage element has a plurality of staging storage elements wherein each of the plurality of staging storage elements corresponds to a different pipeline stage of the data processing system. In another aspect the MISR result is independent of varying memory access times.
摘要翻译：流水线数据处理系统包括具有位于功能电路内的预定电路节点处的多个测试点的功能电路，与数据处理系统的流水线级相关联的至少一个分段存储元件，其被耦合以直接从多个测试点和多输入移位寄存器（MISR），其被耦合以从所述至少一个分段存储元件接收测试数据并提供MISR结果。在一个方面，所述至少一个登台存储元件具有多个分段存储元件，其中所述多个分段存储元件中的每一个对应于所述数据处理系统的不同流水线级。在另一方面，MISR结果与变化的存储器访问时间无关。

10. 发明授权

US06748558B1 Performance monitor system and method suitable for use in an integrated circuit 有权
标题翻译：适用于集成电路的性能监控系统和方法
公开(公告)号：US06748558B1
公开(公告)日：2004-06-08
申请号：US09567973
申请日：2000-05-10
申请人： David R. Gonzales , Brian D. Branson , Jimmy Gumulja , William C. Moyer
发明人： David R. Gonzales , Brian D. Branson , Jimmy Gumulja , William C. Moyer
IPC分类号： G06F1100
CPC分类号： G06F11/3409 , G06F11/349 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A performance monitor system includes a core processor (115), a core processor associated device, such as a cache (123), and first logic, such as performance logic (127). The core processor (115) is operable to execute information. The core processor associated device provides a first signal (CACHE_PERF), which defines performance of the core processor associated device (123) during operation of the core processor (115). The first logic (127) is coupled to the core processor associated device (123) and monitors the first signal (CACHE_PERF) in response to a second signal (WPT0,1), which defines a match of user-settable attributes associated with the operation of the core processor (115).
摘要翻译：性能监视器系统包括核心处理器（115），诸如高速缓存（123）的核心处理器关联设备以及诸如性能逻辑（127）之类的第一逻辑。核心处理器（115）可操作以执行信息。核心处理器相关设备提供第一信号（CACHE_PERF），其在核心处理器（115）的操作期间定义核心处理器相关设备（123）的性能。第一逻辑（127）耦合到核心处理器相关设备（123）并且响应于第二信号（WPT0,1）监视第一信号（CACHE_PERF），其定义与操作相关联的用户可设置属性的匹配的核心处理器（115）。

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