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1. 发明申请

WO2006065698A2 SENSE AMPLIFIER CIRCUITRY AND ARCHITECTURE TO WRITE DATA INTO AND/OR READ FROM MEMORY CELLS 审中-公开
标题翻译： SENSE放大器电路和架构将数据写入和/或从存储器中读取
公开(公告)号：WO2006065698A2
公开(公告)日：2006-06-22
申请号：PCT/US2005/044791
申请日：2005-12-12
申请人： WALLER, William, Kenneth , CARMAN, Eric
发明人： WALLER, William, Kenneth , CARMAN, Eric
IPC分类号： G11C11/24
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/14 , G11C11/4099 , G11C2211/4013 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A technique of, and circuitry for sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, sense amplifier circuitry is relatively compact and pitched to the array of memory cells such that a row of data may be read, sampled and/or sensed during a read operation. In this regard, an entire row of memory cells may be accessed and read during one operation which, relative to at least architecture employing multiplexer circuitry, may minimize, enhance and/or improve read latency and read access time, memory cell disturbance and/or simplify the control of the sense amplifier circuitry and access thereof. The sense amplifier circuitry may include write back circuitry to modify or "re-store" the data read, sampled and/or sensed during a read operation and/or a refresh operation in the context of a DRAM array. The sense amplifier circuitry of this embodiment restores and/or refreshes data in an entire row of volatile and/or destructive read type memory cells in parallel. This architecture may minimize, enhance and/or improve write back and read latency parameters, relative to at least architecture employing multiplexer circuitry. Also, data that has been read, sampled and/or sensed by the sense amplifier circuitry during a read operation may be modified before being written back to one or more of the memory cells of the selected row of the array of memory cells.
摘要翻译：用于采样，感测，读取和/或确定存储器单元阵列的存储器单元的数据状态的技术和电路（例如，具有由电浮体晶体管组成的多个存储单元的存储单元阵列）。在一个实施例中，感测放大器电路相对紧凑并且倾斜到存储器单元阵列，使得在读取操作期间可以读取，采样和/或感测数据行。在这方面，可以在一个操作期间访问和读取整行存储器单元，其相对于至少采用多路复用器电路的架构可以最小化，增强和/或改善读延迟和读访问时间，存储器单元的干扰和/或简化了读出放大器电路的控制及其访问。读出放大器电路可以包括写回电路，以在DRAM阵列的上下文中修改或“重新存储”在读取操作期间和/或刷新操作期间读取，采样和/或感测的数据。该实施例的读出放大器电路并行地在整行的易失性和/或破坏性读取型存储器单元中恢复和/或刷新数据。相对于至少采用多路复用器电路的架构，该架构可以最小化，增强和/或改进回写和读取延迟参数。此外，读取操作期间由读出放大器电路读取，采样和/或感测的数据可以在被写回存储器单元阵列的选定行的一个或多个存储器单元之前被修改。

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