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1. 发明申请

US20080276034A1 Design Structure for Transmitting Data in an Integrated Circuit 审中-公开
标题翻译：集成电路中数据传输的设计结构
公开(公告)号：US20080276034A1
公开(公告)日：2008-11-06
申请号：US12179597
申请日：2008-07-25
申请人： W. Riyon Harding , David W. Milton , Clarence Rosser Ogilvie , Jason E. Rotella , Paul M. Schanely , Sebastian T. Ventrone
发明人： W. Riyon Harding , David W. Milton , Clarence Rosser Ogilvie , Jason E. Rotella , Paul M. Schanely , Sebastian T. Ventrone
IPC分类号： G06F13/00
CPC分类号： G06F17/505
摘要： A design structure, which may be generated by a fabless design company, for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.
摘要翻译：可以由无晶圆厂设计公司生成的用于在驻留在集成电路中的核之间传输数据的设计结构。通过使用位于核心和仲裁器之间的集线器来传输数据。仲裁器维护一个表，其中包含核心之间路由路径的所有有效组合。

2. 发明授权

US07536496B2 Method and apparatus for transmitting data in an integrated circuit 失效
标题翻译：用于在集成电路中传输数据的方法和装置
公开(公告)号：US07536496B2
公开(公告)日：2009-05-19
申请号：US11276449
申请日：2006-02-28
申请人： W. Riyon Harding , David W. Milton , Clarence Rosser Ogilvie , Jason E. Rotella , Paul M. Schanely , Sebastian T. Ventrone
发明人： W. Riyon Harding , David W. Milton , Clarence Rosser Ogilvie , Jason E. Rotella , Paul M. Schanely , Sebastian T. Ventrone
IPC分类号： G06F13/00 , G06F13/42 , G06F13/362 , H04L12/28 , H04L12/56 , H03K17/00
CPC分类号： G06F13/14 , G06F13/362
摘要： A method and apparatus for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.
摘要翻译：一种用于在驻留在集成电路中的核之间传送数据的方法和装置。通过使用位于核心和仲裁器之间的集线器来传输数据。仲裁器维护一个表，其中包含核心之间路由路径的所有有效组合。

3. 发明授权

US07787577B2 Asynchronous interface methods and apparatus 失效
标题翻译：异步接口方法和设备
公开(公告)号：US07787577B2
公开(公告)日：2010-08-31
申请号：US12013958
申请日：2008-01-14
申请人： Seetharam Gundurao , Kenneth Anthony Lauricella , Clarence Rosser Ogilvie , Nishant Sharma , Richard N. Wilson
发明人： Seetharam Gundurao , Kenneth Anthony Lauricella , Clarence Rosser Ogilvie , Nishant Sharma , Richard N. Wilson
IPC分类号： H04L7/00
CPC分类号： H03M9/00 , H04L7/0041 , H04L25/14
摘要： In a first aspect of the invention, a first method is provided for aligning signals from a first receiver located in a first clock domain to a second receiver located in a second clock domain. The first method includes the steps of creating a programmable delay element between the first and second receivers, and selectively adding delay via the programmable delay element to the signals until the signals are aligned. Numerous other aspects are provided.
摘要翻译：在本发明的第一方面，提供了一种第一种方法，用于将来自位于第一时钟域中的第一接收机的信号对准位于第二时钟域中的第二接收机。第一种方法包括以下步骤：在第一和第二接收机之间创建可编程延迟元件，并且经由可编程延迟元件选择性地将延迟添加到信号中直到信号被对准。提供了许多其他方面。

4. 发明授权

US07757032B2 Computer system bus bridge 失效
标题翻译：计算机系统总线桥
公开(公告)号：US07757032B2
公开(公告)日：2010-07-13
申请号：US12195134
申请日：2008-08-20
申请人： Giora Biran , Robert Allen Drehmel , Robert Spencer Horton , Mark E. Kautzman , Jamie Randall Kuesel , Ming-i Mark Lin , Eric Oliver Mejdrich , Clarence Rosser Ogilvie , Charles S. Woodruff
发明人： Giora Biran , Robert Allen Drehmel , Robert Spencer Horton , Mark E. Kautzman , Jamie Randall Kuesel , Ming-i Mark Lin , Eric Oliver Mejdrich , Clarence Rosser Ogilvie , Charles S. Woodruff
IPC分类号： G06F13/36 , G06F3/00
CPC分类号： G06F13/4059 , G06F12/0831
摘要： A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.
摘要翻译：高速计算机总线与高速输出总线之间的总线桥。优选实施例是用于来自国际商业机器公司（IBM）的GPUL PowerPC微处理器的GPUL总线与输出高速接口（MPI）之间的总线桥。另一个优选实施例是多芯片模块上的总线收发器中的总线桥。

5. 发明授权

US06321312B1 System and method for controlling peripheral device memory access in a data processing system 失效
标题翻译：用于在数据处理系统中控制外围设备存储器访问的系统和方法
公开(公告)号：US06321312B1
公开(公告)日：2001-11-20
申请号：US09108896
申请日：1998-07-01
申请人： Gordon Taylor Davis , Llewellyn Bradley Marshall, IV , Clarence Rosser Ogilvie , Paul Colvin Stabler
发明人： Gordon Taylor Davis , Llewellyn Bradley Marshall, IV , Clarence Rosser Ogilvie , Paul Colvin Stabler
IPC分类号： G06F1200
CPC分类号： G06F13/38
摘要： A cache based processing system is provided with a loop detection circuit for detecting the entry into and termination of program loops and for enabling peripheral device access to the main memory after completion of the first pass through the loop and terminating access when the program leaves the loop.
摘要翻译：基于缓存的处理系统设置有环路检测电路，用于检测程序循环的进入和终止，并且用于在完成第一次循环之后使外围设备能够访问主存储器，并且当程序离开循环时终止访问。

6. 发明授权

US07715995B2 Design structure for measurement of power consumption within an integrated circuit 失效
标题翻译：集成电路内功耗测量的设计结构
公开(公告)号：US07715995B2
公开(公告)日：2010-05-11
申请号：US12046501
申请日：2008-03-12
申请人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
发明人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
IPC分类号： G06F19/00
CPC分类号： G01R31/31721
摘要： An design structure for measuring power consumed during operation of an integrated circuit. The design structure including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal.
摘要翻译：一种用于测量集成电路运行期间消耗的功率的设计结构。该设计结构包括：具有输入和输出的数据处理电路，所述数据处理电路被配置为基于输入数据信号产生输出数据信号; 功率测量电路，被配置为测量由所述输入信号产生所述输出信号时由所述处理电路消耗的电力量;连接在所述处理电路和所述处理电路的电源之间的功率测量电路; 以及存储元件，被配置为存储包含表示由处理电路消耗的电力量的值的标签，用于从输入数据信号生成输出数据信号，以及（a）输入数据信号的输入数据或（b ）指向输入数据信号的输入数据的指针。

7. 发明申请

US20090157334A1 MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：在集成电路中测量功耗
公开(公告)号：US20090157334A1
公开(公告)日：2009-06-18
申请号：US11956836
申请日：2007-12-14
申请人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
发明人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
IPC分类号： G06F19/00 , G01R21/00
CPC分类号： H03K19/0008 , G01R31/318575
摘要： An apparatus and method for measuring power consumed during operation of an integrated circuit. The apparatus including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal.
摘要翻译：一种用于测量集成电路操作期间消耗的功率的装置和方法。该装置包括：具有输入和输出的数据处理电路，该数据处理电路被配置为基于输入数据信号产生一个输出数据信号; 功率测量电路，被配置为测量由所述输入信号产生所述输出信号时由所述处理电路消耗的电力量;连接在所述处理电路和所述处理电路的电源之间的功率测量电路; 以及存储元件，被配置为存储包含表示由处理电路消耗的电力量的值的标签，用于从输入数据信号生成输出数据信号，以及（a）输入数据信号的输入数据或（b ）指向输入数据信号的输入数据的指针。

8. 发明授权

US07480888B1 Design structure for facilitating engineering changes in integrated circuits 失效
标题翻译：集成电路工程变更的设计结构
公开(公告)号：US07480888B1
公开(公告)日：2009-01-20
申请号：US12124771
申请日：2008-05-21
申请人： Clarence Rosser Ogilvie , Charles B. Winn , David Wills Milton , Kenneth Anthony Lauricella , Nitin Sharma , Paul Mark Schanely , Robert Dov Herzl , Robert Spencer Horton , Tad Jeffrey Wilder , Douglas P. Nadeau
发明人： Clarence Rosser Ogilvie , Charles B. Winn , David Wills Milton , Kenneth Anthony Lauricella , Nitin Sharma , Paul Mark Schanely , Robert Dov Herzl , Robert Spencer Horton , Tad Jeffrey Wilder , Douglas P. Nadeau
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A design structure embodied in a machine-readable medium is disclosed in one embodiment of the invention as including a flexible logic block to facilitate engineering changes at selected locations within an IC. The flexible logic block has a consistent and identifiable structure such that a simple automated process may be used to reconfigure the structure to perform different logical operations. In certain embodiments, the flexible logic block includes a circuit, such as a multiplexer, having multiple inputs and at least one output. A metal interconnect structure is coupled to the inputs and enables connection of each of the inputs to one of several electrical potentials using a focused-ion-beam (FIB) tool. In this way, the circuit may be configured to perform different logical operations after components in the IC exist in hardware.
摘要翻译：在本发明的一个实施例中公开了体现在机器可读介质中的设计结构，包括用于促进在IC内的选定位置进行工程变更的灵活逻辑块。灵活的逻辑块具有一致且可识别的结构，使得可以使用简单的自动化过程来重新配置结构以执行不同的逻辑操作。在某些实施例中，柔性逻辑块包括具有多个输入和至少一个输出的电路，例如多路复用器。金属互连结构耦合到输入端，并且能够使用聚焦离子束（FIB）工具将每个输入端连接到几个电势之一。以这种方式，电路可以被配置为在硬件中存在IC中的部件之后执行不同的逻辑操作。

9. 发明授权

US07330925B2 Transaction flow control mechanism for a bus bridge 有权
标题翻译：总线桥的交易流控制机制
公开(公告)号：US07330925B2
公开(公告)日：2008-02-12
申请号：US11064722
申请日：2005-02-24
申请人： Clarence Rosser Ogilvie , Charles S. Woodruff
发明人： Clarence Rosser Ogilvie , Charles S. Woodruff
IPC分类号： G06F13/36 , G06F12/00
CPC分类号： G06F13/4059 , G06F12/0831
摘要： A transaction flow control mechanism is disclosed for a bus bridge in a high speed computer system with a high speed interface for a graphics processor. A preferred embodiment provides a flow control mechanism for the bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and a high speed interface. A preferred embodiment of the invention is a bus transceiver on a multi-chip module.
摘要翻译：公开了一种用于具有用于图形处理器的高速接口的高速计算机系统中的总线桥的事务流控制机制。优选实施例提供了用于来自国际商业机器公司（IBM）的GPUL PowerPC微处理器的GPUL总线与高速接口之间的总线桥的流量控制机制。本发明的优选实施例是多芯片模块上的总线收发器。

10. 发明授权

US5918246A Apparatus and method for prefetching data based on information contained in a compiler generated program map 失效
标题翻译：基于编译器生成的程序映射中包含的信息来预取数据的装置和方法
公开(公告)号：US5918246A
公开(公告)日：1999-06-29
申请号：US788870
申请日：1997-01-23
申请人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Wilbur David Pricer , Sebastian Theodore Ventrone
发明人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Wilbur David Pricer , Sebastian Theodore Ventrone
IPC分类号： G06F9/45 , G06F12/08 , G06F12/00 , G06F9/38 , G06F13/00
CPC分类号： G06F8/4442 , G06F12/0862 , G06F2212/6028
摘要： An apparatus and method for pre-loading a cache memory based on information contained in a compiler generated program map are disclosed. The program map is generated by the compiler at the time source code is compiled into object code. For each application program, the user would have this program map stored with the object file. At the beginning of the program execution cycle, the operating system will determine whether or not a program map exists for the application. If a program map exists, the operating system will load the program map into an area of RAM designated as the program map random access memory (RAM). The program map will be used to pre-load the cache with the appropriate data and instructions for the central processing unit (CPU) to process. The program mapping would be the address location of each jump/branch target that the CPU might encounter during the execution cycle. Each of these locations represent a starting point for a new code sequence. At the start of the map will be an identifier field to mark the start of the map. The next field in the program map will provide the entry point of the starting address of the application program. If a particular application program does not have a program map, the program and cache operation will remain unchanged. This feature provides backwards compatibility with existing application programs.
摘要翻译：公开了一种基于编译器生成的程序映射中包含的信息来预加载高速缓冲存储器的装置和方法。程序地图由编译器在源代码被编译成目标代码时生成。对于每个应用程序，用户将该目录文件存储该程序映射。在程序执行周期开始时，操作系统将确定应用程序是否存在程序映射。如果存在程序映射，则操作系统将程序映射加载到指定为程序映射随机存取存储器（RAM）的RAM区域中。程序地图将用于预先加载高速缓存，并具有相应的数据和指令，供中央处理单元（CPU）处理。程序映射将是执行周期中CPU可能遇到的每个跳转/转移目标的地址位置。这些位置中的每一个代表新代码序列的起始点。在地图的开始，将是一个标识符字段来标记地图的开始。程序地图中的下一个字段将提供应用程序起始地址的入口点。如果特定的应用程序没有程序映射，程序和缓存操作将保持不变。此功能提供与现有应用程序的向后兼容性。

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