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1. 发明申请

US20050112796A1 Semiconductor package heat spreaders and fabrication methods therefor 有权
标题翻译：半导体封装散热器及其制造方法
公开(公告)号：US20050112796A1
公开(公告)日：2005-05-26
申请号：US10721916
申请日：2003-11-24
申请人： Virgil Ararao , Il Shim , Seng Chow , Sheila Alvarez
发明人： Virgil Ararao , Il Shim , Seng Chow , Sheila Alvarez
IPC分类号： H01L21/44 , H01L21/48 , H01L23/367
CPC分类号： H01L23/3672 , H01L21/4878 , H01L2224/32225 , H01L2924/15311
摘要： A method for fabricating a semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the panel for receiving a semiconductor therein. The feet extend from respective channel walls for attachment to a substrate.
摘要翻译：提供了从一体金属板制造半导体散热器的方法。整体金属板形成一个面板，通道壁，至少两个脚和至少一个外部反向弯曲。通道壁从面板取决于在通道壁和面板之间限定通道，用于在其中接收半导体。脚从相应的通道壁延伸以附接到基底。

2. 发明申请

US20060012022A1 Integrated circuit die with pedestal 有权
标题翻译：带基座的集成电路管芯
公开(公告)号：US20060012022A1
公开(公告)日：2006-01-19
申请号：US10894561
申请日：2004-07-19
申请人： Virgil Ararao , Il Shim , Seng Chow
发明人： Virgil Ararao , Il Shim , Seng Chow
IPC分类号： H01L23/48 , H01L23/12
CPC分类号： H01L23/3128 , H01L21/563 , H01L24/45 , H01L24/48 , H01L25/0652 , H01L25/0657 , H01L29/0657 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/32265 , H01L2224/33181 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48195 , H01L2224/48227 , H01L2224/73204 , H01L2224/73215 , H01L2224/73257 , H01L2224/73265 , H01L2225/06506 , H01L2225/06555 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/10158 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/19104 , H01L2924/00015 , H01L2924/00012 , H01L2924/00 , H01L2224/0401
摘要： An integrated circuit die is provided having a body portion having a singulation side and a pedestal portion extending from the body portion and having a singulation side coplanar with the singulation side of the body portion.
摘要翻译：提供一种集成电路管芯，其具有主体部分，该主体部分具有单个侧面和从本体部分延伸的基座部分，并且具有与本体部分的单面侧共面的单面侧。

3. 发明申请

US20050046015A1 Array-molded package heat spreader and fabrication method therefor 有权
标题翻译：阵列成型包装散热器及其制造方法
公开(公告)号：US20050046015A1
公开(公告)日：2005-03-03
申请号：US10921377
申请日：2004-08-18
申请人： Il Shim , Kambhampati Ramakrishna , Diane Sahakian , Seng Chow , Dario Filoteo , Virgil Ararao
发明人： Il Shim , Kambhampati Ramakrishna , Diane Sahakian , Seng Chow , Dario Filoteo , Virgil Ararao
IPC分类号： H01L21/56 , H01L23/31 , H01L23/433 , H01L23/495
CPC分类号： H01L24/97 , H01L21/565 , H01L23/3128 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2924/01033 , H01L2924/01079 , H01L2924/10329 , H01L2924/14 , H01L2924/15311 , H01L2924/16251 , H01L2924/181 , H01L2924/00014 , H01L2224/85 , H01L2924/00012 , H01L2924/00
摘要： A method for forming a heat spreader, and the heat spreader formed thereby, are disclosed. An array heat spreader having a plurality of connected heat spreader panels is formed. Slots are formed in opposing sides of the heat spreader panels. Legs are formed on and extending downwardly from each of the heat spreader panels in at least an opposing pair of the slots on the heat spreader panels. The legs are integral with the respective heat spreader panels from which they depend.
摘要翻译：公开了一种形成散热器的方法和由此形成的散热器。形成具有多个连接的散热板的阵列散热器。狭槽形成在散热板的相对侧。在散热器面板上的至少一对相对的槽中，每个散热板上都形成有腿。腿与它们依赖的相应散热器面板是一体的。

4. 发明申请

US20050006668A1 Semiconductor device package 有权
标题翻译：半导体器件封装
公开(公告)号：US20050006668A1
公开(公告)日：2005-01-13
申请号：US10914870
申请日：2004-08-09
申请人： Virgil Ararao , Hermes Apale , Il Shim
发明人： Virgil Ararao , Hermes Apale , Il Shim
IPC分类号： H01L21/56 , H01L23/13 , H01L23/31 , H01L23/495
CPC分类号： H01L23/3121 , H01L21/565 , H01L23/13 , H01L2924/0002 , H01L2924/3511 , H01L2924/00
摘要： An embodiment of the present invention allows mold compound to flow underneath a substrate where the mold compound will remain in place until the process of mold formation is completed. The mold compound of the package will penetrate all available cavities where the mold compound will remain in place and harden. After hardening, the mold compound surrounding a mold anchor will support an anchored area.
摘要翻译：本发明的一个实施方案允许模塑料在基材的下面流动，其中模具化合物将保持就位，直到模具形成过程完成。包装的模具化合物将穿透所有可用的空腔，其中模具化合物将保持在适当位置并硬化。硬化后，围绕模具锚的模具化合物将支撑锚定区域。

5. 发明申请

US20050242428A1 Heat spreader for thermally enhanced semiconductor package 有权
标题翻译：热增强半导体封装散热器
公开(公告)号：US20050242428A1
公开(公告)日：2005-11-03
申请号：US10836916
申请日：2004-04-30
申请人： Il Shim , Sheila Marie Alvarez , Virgil Ararao
发明人： Il Shim , Sheila Marie Alvarez , Virgil Ararao
IPC分类号： H01L23/34 , H01L23/36 , H01L23/433
CPC分类号： H01L23/36 , H01L23/4334 , H01L2224/16 , H01L2224/73253 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/19105
摘要： An electronic device having a substrate carrier is provided. A semiconductor connected to the substrate carrier. A heat spreader having upper and lower surfaces and legs recessed below the lower surface is connected to the substrate carrier. The Z-dimension between the heat spreader and the substrate carrier is maintained over substantially the entire area of the substrate carrier.
摘要翻译：提供具有基板载体的电子装置。连接到衬底载体的半导体。具有在下表面下方凹陷的上表面和下表面和腿的散热器连接到基板载体。散热器和基板载体之间的Z-尺寸维持在基板载体的基本上整个区域上。

6. 发明申请

US20050161780A1 Strip-fabricated flip chip in package and flip chip in system heat spreader assemblies and fabrication methods therefor 有权
标题翻译：带式制造的倒装芯片封装和倒装芯片系统散热器组件及其制造方法
公开(公告)号：US20050161780A1
公开(公告)日：2005-07-28
申请号：US10766746
申请日：2004-01-27
申请人： Tie Wang , Virgil Ararao , Il Shim , Sheila Marie Alvarez
发明人： Tie Wang , Virgil Ararao , Il Shim , Sheila Marie Alvarez
IPC分类号： H01L21/44 , H01L23/02 , H01L23/31 , H01L23/433
CPC分类号： H01L23/3128 , H01L23/4334 , H01L24/97 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/97 , H01L2924/01033 , H01L2924/14 , H01L2924/15311 , H01L2224/81 , H01L2924/00
摘要： A method for fabricating a semiconductor package with a substrate in a strip format is provided. Semiconductor devices are attached in a strip format to the substrate, and a thermal interface material is applied to the semiconductor devices. A flat panel heat spreader is attached to each semiconductor device. The semiconductor devices are encapsulated with open encapsulation, leaving the surface of the flat panel heat spreader opposite the substrate externally exposed. Individual semiconductor packages are then singulated from the strip format.
摘要翻译：提供了一种以条形格式制造具有衬底的半导体封装的方法。半导体器件以条形格式附接到衬底，并且热界面材料被施加到半导体器件。平板式散热器安装在每个半导体器件上。半导体器件用开放封装封装，使平板散热器的表面与外部裸露的衬底相对。然后单独的半导体封装从条形格式分割。

7. 发明申请

US20060252177A1 Semiconductor package with selective underfill and fabrication method therfor 有权
标题翻译：具有选择性底部填充的半导体封装及其制造方法
公开(公告)号：US20060252177A1
公开(公告)日：2006-11-09
申请号：US11121847
申请日：2005-05-03
申请人： Il Shim , Sheila Alvarez , Romeo Alvarez
发明人： Il Shim , Sheila Alvarez , Romeo Alvarez
IPC分类号： H01L21/00
CPC分类号： H01L21/67092 , H01L2224/16245
摘要： A method of manufacturing a semiconductor package includes providing a substrate having a plurality of contacts with solder bump contact areas that are unmasked. A plurality of underfill bumps is formed on the plurality of contacts selectively in the solder bump contact areas. A die having a plurality of solder bumps is positioned on the substrate so the plurality of solder bumps is substantially vertically aligned with the plurality of underfill bumps. The plurality of solder bumps is pressed into the plurality of underfill bumps until the plurality of solder bumps contacts the plurality of contacts. The plurality of solder bumps is reflowed. The die, the plurality of solder bumps, and the plurality of contacts are encapsulated to expose a lower surface of the plurality of contacts.
摘要翻译：制造半导体封装的方法包括提供具有多个触点的衬底，该触点具有未被掩模的焊料凸块接触区域。多个底部填充凸块在焊料凸块接触区域中选择性地形成在多个触点上。具有多个焊料凸块的裸片位于衬底上，使得多个焊料凸块基本上与多个底部填充凸块垂直对齐。多个焊料凸块被压入多个底部填充凸块中，直到多个焊料凸块接触多个触点。多个焊料凸块被回流。模具，多个焊料凸块和多个触点被封装以暴露多个触点的下表面。

8. 发明申请

US20050173783A1 Semiconductor package with passive device integration 有权
标题翻译：半导体封装采用无源器件集成
公开(公告)号：US20050173783A1
公开(公告)日：2005-08-11
申请号：US10773716
申请日：2004-02-05
申请人： Seng Chow , Il Shim , Ming Ying , Byung Ahn
发明人： Seng Chow , Il Shim , Ming Ying , Byung Ahn
IPC分类号： H01L21/56 , H01L21/68 , H01L21/98 , H01L23/31 , H01L23/495 , H01L25/065 , H01L25/16 , H05K3/20 , H05K3/34
CPC分类号： H01L21/568 , H01L21/56 , H01L23/3107 , H01L23/3114 , H01L23/49503 , H01L23/49548 , H01L23/49551 , H01L23/49575 , H01L23/49589 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2224/05554 , H01L2224/16245 , H01L2224/27013 , H01L2224/2919 , H01L2224/32145 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/83051 , H01L2224/83192 , H01L2224/8385 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/06582 , H01L2924/00014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19103 , H01L2924/19105 , H01L2924/19106 , H05K3/202 , H05K3/3442 , H05K2201/09745 , H05K2201/10636 , Y02P70/611 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A system is provided for an integrated circuit package including a leadframe having a lead finger. A groove is formed in a lead finger for a conductive bonding agent and a passive device is placed in the groove to be held by the conductive bonding agent.
摘要翻译：提供一种用于集成电路封装的系统，该集成电路封装包括具有引线指的引线框架。在用于导电粘合剂的引线指中形成凹槽，并且将无源器件放置在沟槽中以由导电粘合剂保持。

9. 发明申请

US20060220209A1 Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides 有权
公开(公告)号：US20060220209A1
公开(公告)日：2006-10-05
申请号：US11395529
申请日：2006-03-31
申请人： Marcos Karnezos , Il Shim , Byung Han , Kambhampati Ramakrishna , Seng Chow
发明人： Marcos Karnezos , Il Shim , Byung Han , Kambhampati Ramakrishna , Seng Chow
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/552 , H01L24/73 , H01L25/03 , H01L25/105 , H01L25/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2224/85013 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2225/1088 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H01L2924/1815 , H01L2924/19105 , H01L2924/19106 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： Stacked package assemblies include first and second stacked packages, each having at least one die affixed to, and electrically interconnected with, a die attach side of the package substrate. One package is inverted in relation to the other; that is, the die attach sides of the package substrates face one another, and the “land” sides of the substrates face away from one another. Z-interconnection of the packages is by wire bonds connecting the first and second package substrates. The assembly is encapsulated in such a way that both the second package substrate (one side of the assembly) and a portion of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. In some embodiments the first package is a chip scale package, and the second package is a land grid array package. Also, methods for making such stacked packages assemblies include steps of providing a cavity molded LGA package, preferably tested as “good”; applying an adhesive onto the surface of the mold cap of the LGA package; providing a singulated CSP; inverting the CSP and placing the inverted CSP onto the adhesive on the LGA mold cap; curing the adhesive; performing a plasma clean; wire bonding to form z-interconnection between the die attach side of the LGA and the land side of the CSP; performing a plasma clean; performing a molding operation to enclose the die attach side of the LGA, the z-interconnection wire bonds and wire loops, the edges of the CSP, and the marginal area on the land side of the CSP, leaving exposed the land side of the LGA substrate and an area of the land side of the CSP substrate located within a marginal area; attaching second level interconnect solder balls to sites on exposed area of the CSP substrate; and (where the LGA package was provided in a strip or array) saw singulating to complete the assembly. In some embodiments one or more additional components are stacked over the land side of the LGA substrate.

10. 发明申请

US20060220210A1 Semiconductor assembly including chip scale package and second substrate and having exposed substrate surfaces on upper and lower sides 有权
公开(公告)号：US20060220210A1
公开(公告)日：2006-10-05
申请号：US11397027
申请日：2006-03-31
申请人： Marcos Karnezos , Il Shim , Byung Han , Kambhampati Ramakrishna , Seng Chow
发明人： Marcos Karnezos , Il Shim , Byung Han , Kambhampati Ramakrishna , Seng Chow
IPC分类号： H01L23/02
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/3135 , H01L23/49575 , H01L23/49833 , H01L23/552 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/162 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06568 , H01L2225/06572 , H01L2225/06586 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/10162 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over the molding of the first package with the first side of the second substrate facing the die attach side of the first package substrate. Accordingly, the die attach sides of the first substrate and the first side of the second substrate face one another, and the “land” sides of the substrates face away from one another. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated in such a way that both the land side of the second substrate (one side of the assembly) and a portion of the land side of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. In some embodiments the first package is a chip scale package. Also, methods for making such stacked packages assemblies include steps of providing singulated CSP; applying an adhesive onto the surface of the molding of the CSP; providing a second substrate having first and second sides; inverting the CSP and placing the inverted CSP onto the first side of the second substrate such that the adhesive contacts the first side of the second substrate; curing the adhesive; performing a plasma clean; wire bonding to form z-interconnection between the first side of the second substrate and the land side of the CSP; performing a plasma clean; performing a molding operation to enclose the first side of the second substrate, the z-interconnection wire bonds and wire loops, the edges of the CSP, and the marginal area on the land side of the CSP, leaving exposed the land side of the second substrate and an area of the land side of the CSP substrate located within a marginal area; attaching second level interconnect solder balls to sites on exposed area of the CSP substrate; and (where the second substrate was provided in a strip or array) saw singulating to complete the assembly. In some embodiments one or more additional components are stacked over the land side of the second substrate.

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