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1. 发明申请

US20130091346A1 Code Updates in Processing Systems 有权
公开(公告)号：US20130091346A1
公开(公告)日：2013-04-11
申请号：US13270593
申请日：2011-10-11
申请人： Vincenzo Condorelli , Silvio Dragone , William Santiago-Fernandez , Tamas Visegrady
发明人： Vincenzo Condorelli , Silvio Dragone , William Santiago-Fernandez , Tamas Visegrady
IPC分类号： G06F15/177
CPC分类号： G06F9/4403 , G05B19/056 , G06F8/63 , G06F8/65 , G06F8/654 , G06F9/4401 , G06F9/44505 , G06F11/1433 , G06F12/0246 , G06F13/4022 , G06F21/575
摘要： A method for updating code images in a system includes booting a first image of a code with a sub-system processor, receiving a second image of the code, performing a security and reliability check of the second image of the code with the sub-system processor, determining whether the security and reliability check of the second image of the code is successful, storing the second image of the code in a first memory device responsive to determining that the security and reliability check of the second image of the code is successful, designating the second image of the code as an active image, and sending the second image of the code to a second memory device, the second memory device communicatively connected with the first memory device and a main processor.

2. 发明授权

US08631058B2 Providing nondeterministic data 失效
标题翻译：提供非确定性数据
公开(公告)号：US08631058B2
公开(公告)日：2014-01-14
申请号：US12915003
申请日：2010-10-28
申请人： Silvio Dragone , Tamas Visegrady , Vincenzo Condorelli
发明人： Silvio Dragone , Tamas Visegrady , Vincenzo Condorelli
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , H01S5/021 , H01S5/041 , H01S5/105 , H01S5/187
摘要： A system and method for providing non-deterministic data for processes executed by non-synchronized processor elements of a fault resilient system is discussed. The steps of the method comprise receiving a request for getting non-deterministic data from a requesting processor element; assigning non-deterministic data generated by an entropy source to the request; and supplying the non-deterministic data assigned to the request, to the requesting processor element.
摘要翻译：讨论了用于为故障恢复系统的非同步处理器元件执行的处理提供非确定性数据的系统和方法。所述方法的步骤包括从请求处理器元件接收获取非确定性数据的请求; 将由熵源产生的非确定性数据分配给所述请求; 以及将分配给该请求的非确定性数据提供给请求处理器元件。

3. 发明申请

US20120278905A1 CONFIGURABLE INTEGRATED TAMPER DECTECTION CIRCUITRY 失效
标题翻译：可配置集成式夯锤保护电路
公开(公告)号：US20120278905A1
公开(公告)日：2012-11-01
申请号：US13096381
申请日：2011-04-28
申请人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
发明人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
IPC分类号： G06F21/02
CPC分类号： G06F21/86
摘要： Tamper detection circuitry includes a first surface layer surrounding a protected memory, the first surface layer comprising a first plurality of conductive sections; a second surface layer surrounding the protected memory, the second surface layer comprising a second plurality of conductive sections; a programmable interconnect located inside the first surface layer, the programmable interconnect being connected to each conductive section by a plurality of conductive traces, the programmable interconnect being configured to group the conductive section of the first and second plurality of conductive sections into a plurality of circuits, each of the plurality of circuits having a different respective voltage; and a tamper detection module, the tamper detection module configured to detect tampering in the event that a conductive section that is part of a first circuit comes into physical contact with a conductive section that is part of a second circuit.
摘要翻译：防篡改检测电路包括围绕受保护存储器的第一表面层，第一表面层包括第一多个导电部分; 围绕被保护的存储器的第二表面层，所述第二表面层包括第二多个导电部分; 位于所述第一表面层内部的可编程互连，所述可编程互连通过多个导电迹线连接到每个导电部分，所述可编程互连配置为将所述第一和第二多个导电部分的导电部分分组成多个电路所述多个电路中的每一个具有不同的相应电压; 以及篡改检测模块，所述篡改检测模块被配置为在作为第一电路的一部分的导电部分与作为第二电路的一部分的导电部分物理接触的情况下检测篡改。

4. 发明授权

US08140792B2 Indirectly-accessed, hardware-affine channel storage in transaction-oriented DMA-intensive environments 失效
标题翻译：在面向事务的DMA密集型环境中间接访问，硬件仿射通道存储
公开(公告)号：US08140792B2
公开(公告)日：2012-03-20
申请号：US12392282
申请日：2009-02-25
申请人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
发明人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
IPC分类号： G06F13/00
CPC分类号： G06F12/1081
摘要： Embodiments of the invention provide a method, system, and computer program product for managing a computer memory system including a channel controller and a memory area. In one embodiment, the method comprises the channel controller receiving a request including a header and a payload, and separating said memory area into a working memory area and an auxiliary memory area. A copy of the header is deposited in the working memory area; and a full copy of the request, including a copy of the header and a copy of the payload, is deposited in the auxiliary memory area. The copy of the request in the auxiliary memory area is used to perform hardware operations; and the copy of the header in the working memory area is used to perform software operations.
摘要翻译：本发明的实施例提供了一种用于管理包括通道控制器和存储区域的计算机存储器系统的方法，系统和计算机程序产品。在一个实施例中，该方法包括信道控制器接收包括头部和有效载荷的请求，并将所述存储区域分成工作存储器区域和辅助存储器区域。标题的副本存放在工作存储器区域中; 并且包括标题的副本和有效载荷的副本的请求的完整副本被存储在辅助存储器区域中。辅助存储器区域中的请求副本用于执行硬件操作; 并且使用工作存储器区域中的标题的副本来执行软件操作。

5. 发明授权

US08613111B2 Configurable integrated tamper detection circuitry 失效
标题翻译：可配置的集成篡改检测电路
公开(公告)号：US08613111B2
公开(公告)日：2013-12-17
申请号：US13096381
申请日：2011-04-28
申请人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
发明人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
IPC分类号： G06F21/00
CPC分类号： G06F21/86
摘要： Tamper detection circuitry includes a first surface layer surrounding a protected memory, the first surface layer comprising a first plurality of conductive sections; a second surface layer surrounding the protected memory, the second surface layer comprising a second plurality of conductive sections; a programmable interconnect located inside the first surface layer, the programmable interconnect being connected to each conductive section by a plurality of conductive traces, the programmable interconnect being configured to group the conductive section of the first and second plurality of conductive sections into a plurality of circuits, each of the plurality of circuits having a different respective voltage; and a tamper detection module, the tamper detection module configured to detect tampering in the event that a conductive section that is part of a first circuit comes into physical contact with a conductive section that is part of a second circuit.
摘要翻译：防篡改检测电路包括围绕受保护存储器的第一表面层，第一表面层包括第一多个导电部分; 围绕被保护的存储器的第二表面层，所述第二表面层包括第二多个导电部分; 位于所述第一表面层内部的可编程互连，所述可编程互连通过多个导电迹线连接到每个导电部分，所述可编程互连配置为将所述第一和第二多个导电部分的导电部分分组成多个电路所述多个电路中的每一个具有不同的相应电压; 以及篡改检测模块，所述篡改检测模块被配置为在作为第一电路的一部分的导电部分与作为第二电路的一部分的导电部分物理接触的情况下检测篡改。

6. 发明申请

US20100217946A1 INDIRECTLY-ACCESSED, HARDWARE-AFFINE CHANNEL STORAGE IN TRANSACTION-ORIENTED DMA-INTENSIVE ENVIRONMENTS 失效
标题翻译：在面向交易的DMA密集环境中的独立访问，硬件自由频道存储
公开(公告)号：US20100217946A1
公开(公告)日：2010-08-26
申请号：US12392282
申请日：2009-02-25
申请人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
发明人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
IPC分类号： G06F12/16
CPC分类号： G06F12/1081
摘要： Embodiments of the invention provide a method, system, and computer program product for managing a computer memory system including a channel controller and a memory area. In one embodiment, the method comprises the channel controller receiving a request including a header and a payload, and separating said memory area into a working memory area and an auxiliary memory area. A copy of the header is deposited in the working memory area; and a full copy of the request, including a copy of the header and a copy of the payload, is deposited in the auxiliary memory area. The copy of the request in the auxiliary memory area is used to perform hardware operations; and the copy of the header in the working memory area is used to perform software operations.
摘要翻译：本发明的实施例提供了一种用于管理包括通道控制器和存储区域的计算机存储器系统的方法，系统和计算机程序产品。在一个实施例中，该方法包括信道控制器接收包括头部和有效载荷的请求，并将所述存储区域分成工作存储器区域和辅助存储器区域。标题的副本存放在工作存储器区域中; 并且包括标题的副本和有效载荷的副本的请求的完整副本被存储在辅助存储器区域中。辅助存储器区域中的请求副本用于执行硬件操作; 并且使用工作存储器区域中的标题的副本来执行软件操作。

7. 发明授权

US09069966B2 Code updates in processing systems 有权
标题翻译：处理系统中的代码更新
公开(公告)号：US09069966B2
公开(公告)日：2015-06-30
申请号：US13270593
申请日：2011-10-11
申请人： Vincenzo Condorelli , Silvio Dragone , William S. Fernandez , Tamas Visegrady
发明人： Vincenzo Condorelli , Silvio Dragone , William S. Fernandez , Tamas Visegrady
IPC分类号： G06F9/00 , G06F15/177 , G06F21/57 , G06F12/02 , G06F9/445 , G06F9/44
CPC分类号： G06F9/4403 , G05B19/056 , G06F8/63 , G06F8/65 , G06F8/654 , G06F9/4401 , G06F9/44505 , G06F11/1433 , G06F12/0246 , G06F13/4022 , G06F21/575
摘要： A method for updating code images in a system includes booting a first image of a code with a sub-system processor, receiving a second image of the code, performing a security and reliability check of the second image of the code with the sub-system processor, determining whether the security and reliability check of the second image of the code is successful, storing the second image of the code in a first memory device responsive to determining that the security and reliability check of the second image of the code is successful, designating the second image of the code as an active image, and sending the second image of the code to a second memory device, the second memory device communicatively connected with the first memory device and a main processor.
摘要翻译：一种用于更新系统中的代码图像的方法包括用子系统处理器引导代码的第一图像，接收代码的第二图像，使用子系统执行代码的第二图像的安全性和可靠性检查处理器，确定代码的第二图像的安全性和可靠性检查是否成功，将代码的第二图像存储在第一存储器设备中，以响应于确定代码的第二图像的安全性和可靠性检查成功，将代码的第二图像指定为活动图像，以及将代码的第二图像发送到第二存储器设备，与第一存储器设备和主处理器通信地连接的第二存储器设备。

8. 发明授权

US08832696B2 Adaptive channel for algorithms with different latency and performance points 有权
标题翻译：具有不同延迟和性能点的算法的自适应通道
公开(公告)号：US08832696B2
公开(公告)日：2014-09-09
申请号：US12976194
申请日：2010-12-22
申请人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
发明人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
IPC分类号： G06F9/46
CPC分类号： G06F9/46 , G06F9/4843
摘要： A method for processing requests in a channel can include receiving a first request in the channel, running calculations on the first request in a processing time TP, in response to a receipt of a plurality of subsequent requests, creating a batch, adding each of the plurality of subsequent requests to the batch and processing the batch in a time TB.
摘要翻译：用于处理信道中的请求的方法可以包括：响应于接收到多个后续请求，在所述信道中接收第一请求，在处理时间TP中对所述第一请求进行计算，创建批次，批次的多个后续请求并在一个时间TB中处理该批次。

9. 发明申请

US20120167097A1 ADAPTIVE CHANNEL FOR ALGORITHMS WITH DIFFERENT LATENCY AND PERFORMANCE POINTS 有权
标题翻译：具有不同的延迟和性能点的算法的自适应通道
公开(公告)号：US20120167097A1
公开(公告)日：2012-06-28
申请号：US12976194
申请日：2010-12-22
申请人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
发明人： Vincenzo Condorelli , Silvio Dragone , Tamas Visegrady
IPC分类号： G06F9/46
CPC分类号： G06F9/46 , G06F9/4843
摘要： A method for processing requests in a channel can include receiving a first request in the channel, running calculations on the first request in a processing time TP, in response to a receipt of a plurality of subsequent requests, creating a batch, adding each of the plurality of subsequent requests to the batch and processing the batch in a time TB.
摘要翻译：用于处理信道中的请求的方法可以包括：响应于接收到多个后续请求，在所述信道中接收第一请求，在处理时间TP中对所述第一请求进行计算，创建批次，批次的多个后续请求并在一个时间TB中处理该批次。

10. 发明申请

US20110106870A1 SYSTEM AND A METHOD FOR PROVIDING NONDETERMINISTIC DATA 失效
标题翻译：系统和提供非法数据的方法
公开(公告)号：US20110106870A1
公开(公告)日：2011-05-05
申请号：US12915003
申请日：2010-10-28
申请人： Silvio Dragone , Tamas Visegrady , Vincenzo Condorelli
发明人： Silvio Dragone , Tamas Visegrady , Vincenzo Condorelli
IPC分类号： G06F7/58 , G06F9/44
CPC分类号： G06F7/588 , H01S5/021 , H01S5/041 , H01S5/105 , H01S5/187
摘要： A system and method for providing non-deterministic data for processes executed by non-synchronized processor elements of a fault resilient system is discussed. The steps of the method comprise receiving a request for getting non-deterministic data from a requesting processor element; assigning non-deterministic data generated by an entropy source to the request; and supplying the non-deterministic data assigned to the request, to the requesting processor element.
摘要翻译：讨论了用于为故障恢复系统的非同步处理器元件执行的处理提供非确定性数据的系统和方法。所述方法的步骤包括从请求处理器元件接收获取非确定性数据的请求; 将由熵源产生的非确定性数据分配给所述请求; 以及将分配给该请求的非确定性数据提供给请求处理器元件。

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