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1. 发明申请

US20150081934A1 SYSTEM AND METHOD FOR DATA SYNCHRONIZATION ACROSS DIGITAL DEVICE INTERFACES 有权
标题翻译：用于数字同步的数字设备接口的系统和方法
公开(公告)号：US20150081934A1
公开(公告)日：2015-03-19
申请号：US14028489
申请日：2013-09-16
申请人： Vinay Gupta , Nir Baruch , Amit Gur
发明人： Vinay Gupta , Nir Baruch , Amit Gur
IPC分类号： G06F5/16
CPC分类号： G06F13/1626 , G06F1/12 , G06F13/00 , G06F13/1673 , G06F13/1689
摘要： A system for synchronizing and re-ordering data transmitted between first and second clock domains associated with first and second device interfaces, respectively, includes a splitter, an arbiter, a transaction manager, and a read data buffer. The splitter receives a parent read request from one or more data input ports of the first device interface and splits it into one or more read requests. The arbiter receives the one or more read requests and selects one of the read requests and transmits it to the transaction manager. The transaction manager allocates an entry to the read request and then the read request is transmitted to the read data buffer. Thereafter, the read data buffer transmits the read request to the second device interface and transmits received response data to the first device interface.
摘要翻译：用于同步和重新排序在与第一和第二设备接口相关联的第一和第二时钟域之间传输的数据的系统分别包括分离器，仲裁器，事务管理器和读取数据缓冲器。分离器从第一设备接口的一个或多个数据输入端口接收父读请求，并将其分解成一个或多个读请求。仲裁器接收一个或多个读取请求，并选择一个读取请求并将其发送到事务管理器。事务管理器将一个条目分配给读取请求，然后读取请求被发送到读取数据缓冲区。此后，读取的数据缓冲器将读取的请求发送到第二设备接口，并将接收到的响应数据发送到第一设备接口。

2. 发明授权

US09292456B2 System and method for data synchronization across digital device interfaces 有权
标题翻译：用于跨数字设备接口进行数据同步的系统和方法
公开(公告)号：US09292456B2
公开(公告)日：2016-03-22
申请号：US14028489
申请日：2013-09-16
申请人： Vinay Gupta , Nir Baruch , Amit Gur
发明人： Vinay Gupta , Nir Baruch , Amit Gur
IPC分类号： G06F13/00 , G06F13/16 , G06F1/12
CPC分类号： G06F13/1626 , G06F1/12 , G06F13/00 , G06F13/1673 , G06F13/1689
摘要： A system for synchronizing and re-ordering data transmitted between first and second clock domains associated with first and second device interfaces, respectively, includes a splitter, an arbiter, a transaction manager, and a read data buffer. The splitter receives a parent read request from one or more data input ports of the first device interface and splits it into one or more read requests. The arbiter receives the one or more read requests and selects one of the read requests and transmits it to the transaction manager. The transaction manager allocates an entry to the read request and then the read request is transmitted to the read data buffer. Thereafter, the read data buffer transmits the read request to the second device interface and transmits received response data to the first device interface.
摘要翻译：用于同步和重新排序在与第一和第二设备接口相关联的第一和第二时钟域之间传输的数据的系统分别包括分离器，仲裁器，事务管理器和读取数据缓冲器。分离器从第一设备接口的一个或多个数据输入端口接收父读请求，并将其分解成一个或多个读请求。仲裁器接收一个或多个读取请求，并选择一个读取请求并将其发送到事务管理器。事务管理器将一个条目分配给读取请求，然后读取请求被发送到读取数据缓冲区。此后，读取的数据缓冲器将读取的请求发送到第二设备接口，并将接收到的响应数据发送到第一设备接口。

3. 发明授权

US09824044B2 Common public radio interface (CPRI) lane controller coupled to direct memory access (DMA) wherein a time division duplex (TDD) steers control of CPRI 有权
公开(公告)号：US09824044B2
公开(公告)日：2017-11-21
申请号：US14759203
申请日：2013-01-10
申请人： Roy Shor , Nir Baruch , Ori Goren , Amit Gur
发明人： Roy Shor , Nir Baruch , Ori Goren , Amit Gur
IPC分类号： G06F13/28 , G06F13/42 , G06F13/24 , H04W88/08
CPC分类号： G06F13/287 , G06F13/24 , G06F13/4282 , H04W88/085
摘要： A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.

4. 发明授权

US09990305B2 Memory management component having multiple memory management modules and method therefor 有权
公开(公告)号：US09990305B2
公开(公告)日：2018-06-05
申请号：US14490902
申请日：2014-09-19
申请人： Nir Baruch , Nir Atzmon , David W. Todd
发明人： Nir Baruch , Nir Atzmon , David W. Todd
IPC分类号： G06F12/1036 , G06F12/1009 , G06F12/14
CPC分类号： G06F12/1036 , G06F12/1009 , G06F12/1441 , G06F2212/657
摘要： A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within a processing system are disclosed. The memory management component comprises a first memory management module arranged to provide memory management functionality for received memory access transactions in accordance with a paging memory management scheme, and at least one further memory management module arranged to provide memory management functionality for received memory access transactions in accordance with an address range memory management scheme.

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