专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6037046A Multi-component electromagnetic wave absorption panels 失效
标题翻译：多分量电磁波吸收面板
公开(公告)号：US6037046A
公开(公告)日：2000-03-14
申请号：US782934
申请日：1997-01-13
申请人： Vikram Joshi , Kenichi Kimura , Carlos A. Paz de Araujo , Hiroshi Kiyokawa
发明人： Vikram Joshi , Kenichi Kimura , Carlos A. Paz de Araujo , Hiroshi Kiyokawa
IPC分类号： E04B1/92 , H01Q17/00 , B32B7/00 , H05K9/00
CPC分类号： E04B1/92 , H01Q17/00 , H01Q17/004 , H01Q17/007 , H01Q17/008 , Y10T428/24942 , Y10T428/252 , Y10T428/31507 , Y10T428/31544 , Y10T428/31678
摘要： An electromagnetic wave absorption panel for use in building construction includes a protective tile layer, an absorber layer, a metal reflective layer, and a building support layer, such as concrete. The absorber layer is multi-component structure, such as: a high dielectric constant layer and ferrite layer; a ferrite layer and a low dielectric constant layer; a ferrite and a polymer; a polymer and a material having a higher dielectric constant than the polymer; a ferroelectric, a ferrite, and a polymer; a ferrite, a polymer, and a high dielectric constant material; and a high dielectric constant material, a material in which the imaginary part of the permeability is greater than or equal to the real part of the permeability, and a low dielectric constant material. The invention also includes combinations of the above, such as: a high dielectric constant material, a ferrite, and a low dielectric constant material; and multiple layers of a ferrite and a polymer. The invention further includes the above structures and combinations with specific materials, such as a ferrite, a polymer, LSM, and a high dielectric constant material; and a ferrite, a polymer, and BST. The invention also includes: a multi-component absorber element having an effective real part of the permitivity, .epsilon.'.sub.eff, and an effective real part of the permeability, .mu.'.sub.eff, such that (.epsilon.'.sub.eff .mu.'.sub.eff).sup.1/2 .about.1/f over said range of frequencies, where f is the frequency of the incident wave; and a multi-component absorber element having an effective real part of the permitivity, .epsilon.'.sub.eff, that decreases with frequency.
摘要翻译：用于建筑结构的电磁波吸收面板包括保护砖层，吸收层，金属反射层和建筑物支撑层，例如混凝土。吸收层是多组分结构，如：高介电常数层和铁素体层; 铁素体层和低介电常数层; 铁氧体和聚合物; 聚合物和具有比聚合物更高的介电常数的材料; 铁电体，铁氧体和聚合物; 铁氧体，聚合物和高介电常数材料; 和高介电常数材料，其中导磁率的虚部大于或等于导磁率的实部的材料和低介电常数材料。本发明还包括上述的组合，例如：高介电常数材料，铁素体和低介电常数材料; 和多层铁素体和聚合物。本发明还包括上述结构和与特定材料的组合，例如铁氧体，聚合物，LSM和高介电常数材料; 和铁素体，聚合物和BST。本发明还包括：多组分吸收元件，其具有有效实部的介电常数εεeff和渗透率μeff的有效实部，使得（ε'eff mu eff）+ E，在所述频率范围内，1/2 + EE差分1 / f，其中f是入射波的频率; 以及多分量吸收元件，其具有随频率而减小的有效实部的ε，εeff。

2. 发明授权

US5853889A Materials for electromagnetic wave absorption panels 失效
标题翻译：电磁波吸收面板材料
公开(公告)号：US5853889A
公开(公告)日：1998-12-29
申请号：US782938
申请日：1997-01-13
申请人： Vikram Joshi , Kenichi Kimura , Carlos A. Paz de Araujo , Hiroshi Kiyokawa
发明人： Vikram Joshi , Kenichi Kimura , Carlos A. Paz de Araujo , Hiroshi Kiyokawa
IPC分类号： E04B1/92 , H01Q17/00 , B32B9/00
CPC分类号： E04B1/92 , H01Q17/00 , H01Q17/004 , H01Q17/007 , H01Q17/008 , Y10S428/913 , Y10T428/12007 , Y10T428/12014 , Y10T428/163 , Y10T428/166 , Y10T428/24612 , Y10T428/24777 , Y10T428/24917 , Y10T428/31504 , Y10T428/31529
摘要： An electromagnetic wave absorption panel for use in building construction includes a protective tile layer, an absorber layer, a metal reflective layer, and a building support layer, such as concrete. The absorber layer utilizes novel materials including high dielectric constant materials, such as ABO.sub.3 type perovskites, layered superlattice materials, conducting oxides, and signet magnetics, ferroelectrics, such as ABO.sub.3 type perovskites and layered superlattice materials, garnets, a nickel-zinc ferrite, Ni.sub.0.4 Zn.sub.0.6 Fe.sub.2 O.sub.4, and polymer-ceramic composites of the above materials.
摘要翻译：用于建筑结构的电磁波吸收面板包括保护砖层，吸收层，金属反射层和建筑物支撑层，例如混凝土。吸收层采用新型材料，包括高介电常数材料，如ABO3型钙钛矿，层状超晶格材料，导电氧化物和印刷磁性材料，铁电体，如ABO3型钙钛矿和层状超晶格材料，石榴石，镍锌铁氧体，Ni0 .4Zn0.6Fe2O4，以及上述材料的聚合物 - 陶瓷复合材料。

3. 发明授权

US06924997B2 Ferroelectric memory and method of operating same 有权
标题翻译：铁电存储器和操作方法相同
公开(公告)号：US06924997B2
公开(公告)日：2005-08-02
申请号：US10381235
申请日：2001-09-25
申请人： Zheng Chen , Vikram Joshi , Myoungho Lim , Carlos A. Paz de Araujo , Larry D. McMillan , Yoshihisa Kato , Tatsuo Otsuki , Yasuhiro Shimada
发明人： Zheng Chen , Vikram Joshi , Myoungho Lim , Carlos A. Paz de Araujo , Larry D. McMillan , Yoshihisa Kato , Tatsuo Otsuki , Yasuhiro Shimada
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory 636 includes a group of memory cells (645, 12, 201, 301, 401, 501), each cell having a ferroelectric memory element (44, 218, etc.), a drive line (122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch (14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch (16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.
摘要翻译：铁电存储器636包括一组存储单元（645,12,21,301,401,501），每个单元具有铁电存储元件（44,218等），驱动线（122,322,422， 522等），在其上放置用于将信息写入到存储器单元组的电压，位线（25,49,125,325,425,525等），其中要从该组存储器单元读出的信息放置存储器单元，在存储器单元和位线之间的前置放大器（20,42,120,320,420等），连接在存储器单元之间的设定开关（14,114,314,414,514等）驱动线和存储器单元，以及与前置放大器并联连接到存储器单元的复位开关（16,116,316,416,516等）。通过将小于铁电存储元件的矫顽电压的电压放置在存储元件上来读取存储器。在读取之前，通过使铁电存储元件的两个电极接地来放电来自该组电池的噪声。

4. 发明授权

US06867452B2 Interlayer oxide containing thin films for high dielectric constant application of the formula AB2O6 or AB2O7 失效
标题翻译：含有氧化物的薄膜用于高介电常数应用的AB2O6或AB2O7
公开(公告)号：US06867452B2
公开(公告)日：2005-03-15
申请号：US10278581
申请日：2002-10-23
申请人： Shinichiro Hayashi , Vikram Joshi , Narayan Solayappan , Joseph D. Cuchiaro , Carlos A. Paz de Araujo
发明人： Shinichiro Hayashi , Vikram Joshi , Narayan Solayappan , Joseph D. Cuchiaro , Carlos A. Paz de Araujo
IPC分类号： H01L21/314 , H01L21/316 , H01L27/06 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/02197 , H01L21/02205 , H01L21/02282 , H01L21/02348 , H01L21/31691 , H01L27/0629
摘要： A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of Bi2O3 with an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulas AB2O6, A2B2O7 and A2Bi2B2O10, wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (BaxSr1−x)(TayNb1−y)2O6, where 0≦y≦1.0 and 0≦y≦1.0; (BaxSr1−x)2(TayNb1−y)2O7, where 0≦x≦1.0 and 0≦y≦1.0; and (BaxSr1−x)2Bi2(TayNb1−y)2O10, where 0≦x≦1.0 and 0≦y≦1.0. Thin films according to the invention have a relative dielectric constant ≧40, and preferably about 100. The value of Vcc in the metal oxides of the invention is close to zero. The value of Tcc is
摘要翻译：一种高介电常数绝缘体，包括选自钨青铜型氧化物，烧绿石型氧化物和Bi 2 O 3与选自钙钛矿和烧绿石型氧化物的氧化物的组合的金属氧化物的薄膜。一个实施方案包含由一般化学计量式AB2O6，A2B2O7和A2B2B2O10表示的金属氧化物，其中A表示选自由Ba，Bi，Sr，Pb，Ca，K，Na和La组成的金属组中的A位原子; B表示选自由Ti，Zr，Ta，Hf，Mo，W和Nb组成的金属组中的B位原子。优选地，金属氧化物是（BaxSr1-x）（TayNb1-y）2O6，其中0 <= y <= 1.0且0 <= Y＆LE; 1.0; （BAxSr1-x）2（TayNb1-y）2O7，其中0 <= x <= 1.0且0 <= y <= 1.0; AND（BAxSr1-x）2Bi2（TayNb1-y）2O10，其中0 <= x <= 1.0且0 <= y <= 1.0。根据本发明的薄膜的相对介电常数> 40，优选约100。本发明的金属氧化物中的Vcc值接近零。 Tcc的值<1000ppm，优选<100。

5. 发明授权

US06781184B2 Barrier layers for protecting metal oxides from hydrogen degradation 有权
标题翻译：用于保护金属氧化物免受氢降解的阻挡层
公开(公告)号：US06781184B2
公开(公告)日：2004-08-24
申请号：US09998469
申请日：2001-11-29
申请人： Narayan Solayappan , Jolanta Celinska , Vikram Joshi , Carlos A. Paz de Araujo , Larry D. McMillan
发明人： Narayan Solayappan , Jolanta Celinska , Vikram Joshi , Carlos A. Paz de Araujo , Larry D. McMillan
IPC分类号： H01L27108
CPC分类号： H01L28/57 , H01L23/642 , H01L2924/0002 , H01L2924/00
摘要： A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450° C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.
摘要翻译：集成电路中的氢扩散阻挡层位于集成电路中以抑制氢扩散到诸如铁电层状超晶格材料的金属氧化物的薄膜。氢扩散阻挡层包括以下化合物中的至少一种：钽酸锶，钽酸铋，氧化钽，氧化钛，氧化锆和氧化铝。氢阻挡层是无定形的，并且在450℃或更低的温度下通过MOCVD工艺制成。在与所述氢扩散阻挡层相邻的地方形成包括选自氮化硅和所述氢阻挡层材料之一的结晶形式的材料的补充氢阻挡层。

6. 发明授权

US06541279B2 Method for forming an integrated circuit 有权
标题翻译：集成电路形成方法
公开(公告)号：US06541279B2
公开(公告)日：2003-04-01
申请号：US09798310
申请日：2001-03-02
申请人： Shinichiro Hayashi , Vikram Joshi , Narayan Solayappan , Joseph D. Cuchiaro , Carlos A. Paz de Araujo
发明人： Shinichiro Hayashi , Vikram Joshi , Narayan Solayappan , Joseph D. Cuchiaro , Carlos A. Paz de Araujo
IPC分类号： H01L2100
CPC分类号： H01L21/02197 , H01L21/02205 , H01L21/02282 , H01L21/02348 , H01L21/31691 , H01L27/0629
摘要： A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of Bi2O3 with an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulas AB2O6, A2B2O7 and A2Bi2B2O10, wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (BaxSr1−x)(TayNb1−y)2O6, where 0≦x≦1.0 and 0≦y≦1.0; (BaxSr1−x)2(TayNb1−y)2O7, where 0≦x≦1.0 and 0≦y≦1.0; and (BaxSr1−x)2Bi2(TayNby−1)2O10, where 0≦x≦1.0 and 0≦y≦1.0. Thin films according to the invention have a relative dielectric constant ≧40, and preferably about 100. The value of Vcc in the metal oxides of the invention is close to zero. The value of Tcc is
摘要翻译：一种高介电常数绝缘体，包括选自钨青铜型氧化物，烧绿石型氧化物和Bi 2 O 3与选自钙钛矿和烧绿石型氧化物的氧化物的组合的金属氧化物的薄膜。一个实施方案包含由一般化学计量式AB2O6，A2B2O7和A2B2B2O10表示的金属氧化物，其中A表示选自由Ba，Bi，Sr，Pb，Ca，K，Na和La组成的金属组中的A位原子; B表示选自由Ti，Zr，Ta，Hf，Mo，W和Nb组成的金属组中的B位原子。优选地，金属氧化物是（BaxSr1-x）（TayNb1-y）2O6，其中0 <= x <= 1.0且0 <= y <= 1.0; （BaxSr1-x）2（TayNb1-y）2O7，其中0 <= x <= 1.0且0 <= y <= 1.0; 和（BaxSr1-x）2Bi2（TayNby-1）2O10，其中0 <= x <= 1.0且0 <= y <= 1.0。根据本发明的薄膜的相对介电常数> 40，优选约100.本发明金属氧化物中的Vcc值接近零。 Tcc的值<1000ppm，优选<100。

7. 发明授权

US06370056B1 Ferroelectric memory and method of operating same 失效
标题翻译：铁电存储器和操作方法相同
公开(公告)号：US06370056B1
公开(公告)日：2002-04-09
申请号：US09523492
申请日：2000-03-10
申请人： Zheng Chen , Vikram Joshi , Myoungho Lim , Carlos A. Paz de Araujo , Larry D. McMillan
发明人： Zheng Chen , Vikram Joshi , Myoungho Lim , Carlos A. Paz de Araujo , Larry D. McMillan
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric non-volatile memory comprising: a plurality of memory cells, each containing an FeFET and a MOSFET, each of said FeFETs having a source, a drain, a substrate, and a gate, and each MOSFET having a pair of source/drains and a gate. The cells are arranged in an array comprising a plurality of rows and a plurality of columns. A gate line and a bit line are associated with each column, and a word line, a drain line, and a substrate line are associated with each row. One source/drain of each MOSFET is connected to its corresponding gate line; the other source/drain is connected to the gate of the FeFET in the cell. The gate of the MOSFET is connected to its corresponding word line which provides a write and erase enable signal. The drain of the FeFET is connected to its corresponding drain line, and the source of the FeFET is connected to its corresponding bit line. The substrate of each FeFET is connected to its corresponding substrate line. A read MOSFET is connected between a drain input and the drain line associated with each row. The gate of the read MOSFET is connected to an input for the read enable signal.
摘要翻译：一种铁电非易失性存储器，包括：多个存储单元，每个存储单元包含FeFET和MOSFET，每个所述FeFET具有源极，漏极，衬底和栅极，并且每个MOSFET具有一对源极/漏极和一个门。单元被布置成包括多行和多列的阵列。栅极线和位线与每列相关联，并且字线，漏极线和衬底线与每一行相关联。每个MOSFET的一个源极/漏极连接到其对应的栅极线; 另一个源极/漏极连接到电池中的FeFET的栅极。 MOSFET的栅极连接到提供写和擦除使能信号的相应字线。 FeFET的漏极连接到其对应的漏极线，并且FeFET的源极连接到其对应的位线。每个FeFET的衬底连接到其相应的衬底线。读取MOSFET连接在与每行相关联的漏极输入和漏极线之间。读取MOSFET的栅极连接到读使能信号的输入端。

8. 发明授权

US07075134B2 Ferroelectric and high dielectric constant integrated circuit capacitors with three-dimensional orientation for high-density memories, and method of making the same 有权
公开(公告)号：US07075134B2
公开(公告)日：2006-07-11
申请号：US10626413
申请日：2003-07-24
申请人： Carlos A. Paz de Araujo , Larry D. McMillan , Narayan Solayappan , Vikram Joshi
发明人： Carlos A. Paz de Araujo , Larry D. McMillan , Narayan Solayappan , Vikram Joshi
IPC分类号： H01L31/119 , H01L27/108
CPC分类号： H01L27/11502 , C30B29/32 , C30B29/68 , G11C11/22 , H01L21/7687 , H01L23/642 , H01L27/11507 , H01L28/55 , H01L28/57 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.

9. 发明授权

US06815223B2 Low thermal budget fabrication of ferroelectric memory using RTP 有权
公开(公告)号：US06815223B2
公开(公告)日：2004-11-09
申请号：US10302441
申请日：2002-11-22
申请人： Jolanta Celinska , Vikram Joshi , Narayan Solayappan , Myoungho Lim , Larry D. McMillan , Carlos A. Paz de Araujo
发明人： Jolanta Celinska , Vikram Joshi , Narayan Solayappan , Myoungho Lim , Larry D. McMillan , Carlos A. Paz de Araujo
IPC分类号： H01G706
CPC分类号： H01L28/55 , C30B29/32 , C30B29/68
摘要： A precursor for forming a thin film of layered superlattice material is applied to an integrated circuit substrate. The precursor coating is heated using rapid thermal processing (RTP) with a ramping rate of 100° C./second at a hold temperature in a range of from 500° C. to 900° C. for a cumulative heating time not exceeding 30 minutes, and preferably less than 5 minutes. In fabricating a ferroelectric memory cell, the coating is heated in oxygen using RTP, then a top electrode layer is formed, and then the substrate including the coating is heated using RTP in oxygen or in nonreactive gas after forming the top electrode layer. The thin film of layered superlattice material preferably comprises strontium bismuth tantalate or strontium bismuth tantalum niobate, and preferably has a thickness in a range of from 25 nm to 120 nm. The process of fabricating a thin film of layered superlattice material typically has a thermal budget value not exceeding 960,000° C.-sec, preferably less than 50,000° C.-sec.

10. 发明授权

US06559469B1 Ferroelectric and high dielectric constant transistors 失效
标题翻译：铁电和高介电常数晶体管
公开(公告)号：US06559469B1
公开(公告)日：2003-05-06
申请号：US09686552
申请日：2000-10-11
申请人： Carlos A. Paz de Araujo , Larry D. McMillan , Vikram Joshi , Narayan Solayappan , Joseph D. Cuchiaro
发明人： Carlos A. Paz de Araujo , Larry D. McMillan , Vikram Joshi , Narayan Solayappan , Joseph D. Cuchiaro
IPC分类号： H01L2972
CPC分类号： H01L27/11502 , C23C16/448 , C23C16/45561 , C23C18/1216 , C23C18/14 , C30B7/00 , C30B7/005 , C30B29/68 , G11C11/22 , G11C11/223 , H01L21/31691 , H01L27/10805 , H01L28/55 , H01L28/60
摘要： An integrated circuit includes a layered superlattice material having the formula A1w1+a1A2w2+a2 . . . Ajwj+ajS1x1+s1S2x2+s2 . . . Skxk+skB1y1+b1B2y2+b2 . . . Blyl+blQz−q, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . B1 represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in ferroelectric FETs in non-volatile memories. Others are high dielectric constant materials that do not degrade or break down over long periods of use and are applied as the gate insulator in volatile memories.
摘要翻译：集成电路包括具有公式A1w1 + a1A2w2 + a2的分层超晶格材料。。。 Ajwj + ajS1x1 + s1S2x2 + s2。。。 Skxk + skB1y1 + b1B2y2 + b2。。。 Blyl + blQz-q，其中A1，A2。。。 Aj代表钙钛矿结构中的A位元素，S1，S2。。。 Sk代表超晶格发生器元件B1，B2。。。 B1表示钙钛矿结构中的B位元素，Q表示阴离子，上标表示各元素的化合价，下标表示单元中元素的原子数，并且至少w1和y1为非零。这些材料中的一些是非常低的疲劳铁电体，并且被应用在非易失性存储器中的铁电FET中。其他的是高介电常数材料，其在长期使用中不会劣化或分解，并且作为在绝缘体中的栅绝缘体。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式