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1. 发明授权

US06930027B2 Method of manufacturing a semiconductor component 有权
标题翻译：制造半导体部件的方法
公开(公告)号：US06930027B2
公开(公告)日：2005-08-16
申请号：US10369874
申请日：2003-02-18
申请人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose , Todd Roggenbauer , Paul Hui , Michael C. Butner
发明人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose , Todd Roggenbauer , Paul Hui , Michael C. Butner
IPC分类号： H01L21/308 , H01L21/762 , H01L21/425
CPC分类号： H01L21/3081 , H01L21/76229
摘要： A method of manufacturing a semiconductor component includes forming a first electrically insulating layer (120) and a second electrically insulating layer (130) over a semiconductor substrate (110). The method further includes etching a first trench (140) and a second trench (150) through the first and second electrically insulating layers and into the semiconductor substrate, and etching a third trench (610) through a bottom surface of the second trench and into the semiconductor substrate. The third trench has a first portion (920) and a second portion (930) interior to the first portion. The method still further includes forming a third electrically insulating layer (910) filling the first trench and the first portion of the third trench without filling the second portion of the third trench, and also includes forming a plug layer (1010) in the second portion of the third trench.
摘要翻译：制造半导体部件的方法包括在半导体衬底（110）上形成第一电绝缘层（120）和第二电绝缘层（130）。该方法还包括通过第一和第二电绝缘层蚀刻第一沟槽（140）和第二沟槽（150）并进入半导体衬底，以及通过第二沟槽的底表面蚀刻第三沟槽（610）并且进入半导体衬底。第三沟槽在第一部分内部具有第一部分（920）和第二部分（930）。该方法还包括形成填充第一沟槽和第三沟槽的第一部分的第三电绝缘层（910），而不填充第三沟槽的第二部分，并且还包括在第二部分中形成插塞层（1010）的第三沟。

2. 发明授权

US06734524B1 Electronic component and method of manufacturing same 有权
标题翻译：电子元件及其制造方法
公开(公告)号：US06734524B1
公开(公告)日：2004-05-11
申请号：US10335030
申请日：2002-12-31
申请人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose , Todd Roggenbauer , Paul Hui
发明人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose , Todd Roggenbauer , Paul Hui
IPC分类号： H01L2900
CPC分类号： H01L27/088 , H01L21/76232
摘要： An electronic component includes a semiconductor substrate (110), an epitaxial semiconductor layer (120, 221, 222) over the semiconductor substrate, and a semiconductor region (130, 230) in the epitaxial semiconductor layer. The epitaxial semiconductor layer has an upper surface (123). A first portion (121) of the epitaxial semiconductor layer is located below the semiconductor region, and a second portion (122) of the epitaxial semiconductor layer is located above the semiconductor region. The semiconductor substrate and the first portion of the epitaxial semiconductor layer have a first conductivity type, and the semiconductor region has a second conductivity type. At least one electrically insulating trench (140, 240) extends from the upper surface of the epitaxial semiconductor layer into at least a portion of the semiconductor region. The semiconductor substrate has a doping concentration higher than a doping concentration of the first portion of the epitaxial semiconductor layer.
摘要翻译：电子部件包括半导体衬底（110），半导体衬底上的外延半导体层（120,221,222）以及外延半导体层中的半导体区域（130,230）。外延半导体层具有上表面（123）。外延半导体层的第一部分（121）位于半导体区域的下方，并且外延半导体层的第二部分（122）位于半导体区域的上方。半导体衬底和外延半导体层的第一部分具有第一导电类型，并且半导体区域具有第二导电类型。至少一个电绝缘沟槽（140,240）从外延半导体层的上表面延伸到半导体区域的至少一部分。半导体衬底的掺杂浓度高于外延半导体层的第一部分的掺杂浓度。

3. 发明申请

US20060014342A1 Method of manufacturing a semiconductor component 有权
标题翻译：制造半导体部件的方法
公开(公告)号：US20060014342A1
公开(公告)日：2006-01-19
申请号：US11182597
申请日：2005-07-14
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd Roggenbauer
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd Roggenbauer
IPC分类号： H01L21/8234 , H01L21/8222 , H01L21/20
CPC分类号： H01L29/866 , H01L27/0255 , H01L27/0814 , Y10S438/983
摘要： A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.
摘要翻译：半导体部件包括第一半导体区域（110,310），第一半导体区域上方的第二半导体区域（120,320），第二半导体区域上方的第三半导体区域（130,330），第四半导体区域（140,320），340），在所述第二半导体区域上方并且与所述第四半导体区域至少部分邻接的第五半导体区域（150,350），在所述第三半导体区域上方的第六半导体区域（160,360），并且电气短路到所述第五半导体区域半导体区域，以及位于第四半导体区域和第五半导体区域上方的电绝缘层（180,380）。在第四半导体区域和第五半导体区域之间的结（145,345）形成仅位于电绝缘层下方的齐纳二极管结。在一个实施例中，第七半导体区域（170）围绕第三，第四，第五和第六半导体区域。

4. 发明申请

US20070224738A1 Semiconductor device with a multi-plate isolation structure 有权
标题翻译：具有多板隔离结构的半导体器件
公开(公告)号：US20070224738A1
公开(公告)日：2007-09-27
申请号：US11390918
申请日：2006-03-27
申请人： Vishnu Khemka , Amitava Bose , Todd Roggenbauer , Ronghua Zhu
发明人： Vishnu Khemka , Amitava Bose , Todd Roggenbauer , Ronghua Zhu
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L21/823878 , H01L21/763 , H01L21/764 , H01L21/823481
摘要： A microelectronic assembly and a method for constructing a microelectronic assembly are provided. The microelectronic assembly may include a semiconductor substrate with an isolation trench (62) formed therein. The isolation trench (62) may have first and second opposing inner walls (74, 76) and a floor (78). First and second conductive plates (106) may be formed over the first and second opposing inner walls (74, 76) of the isolation trench (62) respectively such that there is a gap (90) between the first and second conductive plates (106). First and second semiconductor devices (114) may be formed in the semiconductor substrate on opposing sides of the isolation trench (62). The method may include forming a trench (62) in a semiconductor substrate, forming first and second conductive plates (106) within the trench, and forming first and second semiconductor devices (114) in the semiconductor substrate on opposing sides of the trench (62).
摘要翻译：提供微电子组件和构造微电子组件的方法。微电子组件可以包括其中形成有隔离沟槽（62）的半导体衬底。隔离沟槽（62）可以具有第一和第二相对的内壁（74,76）和底板（78）。第一和第二导电板（106）可以分别形成在隔离沟槽（62）的第一和第二相对的内壁（74,76）上，使得在第一和第二导电板（106）之间存在间隙（90））。可以在隔离沟槽（62）的相对侧上的半导体衬底中形成第一和第二半导体器件（114）。该方法可以包括在半导体衬底中形成沟槽（62），在沟槽内形成第一和第二导电板（106），并且在沟槽（62）的相对侧上的半导体衬底中形成第一和第二半导体器件（114））。

5. 发明申请

US20070221967A1 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US20070221967A1
公开(公告)日：2007-09-27
申请号：US11390796
申请日：2006-03-27
申请人： Vishnu Khemka , Amitava Bose , Todd Roggenbauer , Ronghua Zhu
发明人： Vishnu Khemka , Amitava Bose , Todd Roggenbauer , Ronghua Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/1045 , H01L29/1083 , H01L29/7816
摘要： A semiconductor device may include a semiconductor substrate having a first dopant type. A first semiconductor region within the semiconductor substrate may have a plurality of first and second portions (44, 54). The first portions (44) may have a first thickness, and the second portions (54) may have a second thickness. The first semiconductor region may have a second dopant type. A plurality of second semiconductor regions (42) within the semiconductor substrate may each be positioned at least one of directly below and directly above a respective one of the first portions (44) of the first semiconductor region and laterally between a respective pair of the second portions (54) of the first semiconductor region. A third semiconductor region (56) within the semiconductor substrate may have the first dopant type. A gate electrode (64) may be over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region (56).
摘要翻译：半导体器件可以包括具有第一掺杂剂类型的半导体衬底。半导体衬底内的第一半导体区域可以具有多个第一和第二部分（44,45）。第一部分（44）可以具有第一厚度，并且第二部分（54）可以具有第二厚度。第一半导体区域可以具有第二掺杂剂类型。半导体衬底内的多个第二半导体区域（42）可以各自定位在第一半导体区域的第一部分（44）的相应一个的正下方并直接位于第一半导体区域的第一部分（44）的下方中的至少一个，并且横向地位于相应的一对第二半导体区域第一半导体区域的部分（54）。半导体衬底内的第三半导体区域（56）可以具有第一掺杂剂类型。栅电极（64）可以在第一半导体区域的至少一部分和第三半导体区域（56）的至少一部分之上。

6. 发明申请

US20070200136A1 Isolated zener diodes 审中-公开
标题翻译：隔离齐纳二极管
公开(公告)号：US20070200136A1
公开(公告)日：2007-08-30
申请号：US11364769
申请日：2006-02-28
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd Roggenbauer
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd Roggenbauer
IPC分类号： H01L29/00
CPC分类号： H01L29/866 , H01L29/0692
摘要： The present disclosure relates to isolated Zener diodes (100) that are substantially free of substrate current injection when forward biased. In particular, the Zener diodes (100) include an “isolation tub” structure that includes surrounding walls (150, 195) and a base (130) formed of semiconductor regions. In addition, the diodes (100) include silicide block (260) extending between anode (210) and cathode (220) regions. The reduction or elimination of substrate current injection overcomes a significant shortcoming of conventional Zener diodes that generally all suffer from substrate current injection when they are forward biased. Due to this substrate current injection, the current from each of a conventional diode's two terminals is not the same.
摘要翻译：本公开涉及在正向偏置时基本上不含衬底电流注入的隔离齐纳二极管（100）。特别地，齐纳二极管（100）包括包括由半导体区形成的周围壁（150,195）和基座（130）的“隔离桶”结构。此外，二极管（100）包括在阳极（210）和阴极（220）区域之间延伸的硅化物块（260）。衬底电流注入的减少或消除克服了常规齐纳二极管的显着缺点，当它们正向偏置时，其通常都遭受衬底电流注入。由于这种衬底电流注入，来自常规二极管的两个端子中的每一个的电流是不相同的。

7. 发明申请

US20070200184A1 Methods and apparatus for a stepped-drift MOSFET 有权
标题翻译：梯形漂移MOSFET的方法和装置
公开(公告)号：US20070200184A1
公开(公告)日：2007-08-30
申请号：US11361624
申请日：2006-02-24
申请人： Ronghua Zhu , Amitava Bose , Vishnu Khemka , Todd Roggenbauer
发明人： Ronghua Zhu , Amitava Bose , Vishnu Khemka , Todd Roggenbauer
IPC分类号： H01L29/76 , H01L21/332
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/1083 , H01L29/456 , H01L29/66659 , H01L29/66681 , H01L29/7816
摘要： A power metal-oxide-semiconductor field effect transistor (MOSFET) (100) incorporates a stepped drift region including a shallow trench insulator (STI) (112) partially overlapped by the gate (114) and which extends a portion of the distance to a drain region (122). A silicide block extends from and partially overlaps STI (112) and drain region (122). The STI (112) has a width that is approximately 50% to 75% of the drift region.
摘要翻译：功率金属氧化物半导体场效应晶体管（MOSFET）（100）包括阶梯状漂移区域，其包括与栅极（114）部分重叠的浅沟槽绝缘体（112），并将距离的一部分延伸到漏区（122）。硅化物块从STI（112）和漏极区（122）延伸并部分重叠。 STI（112）的宽度为漂移区域的大约50％至75％。

8. 发明申请

US20060261408A1 Structure and method for RESURF LDMOSFET with a current diverter 有权
标题翻译：具有电流分流器的RESURF LDMOSFET的结构和方法
公开(公告)号：US20060261408A1
公开(公告)日：2006-11-23
申请号：US11363901
申请日：2006-02-28
申请人： Vishnu Khemka , Amitava Bose , Todd Roggenbauer , Ronghua Zhu
发明人： Vishnu Khemka , Amitava Bose , Todd Roggenbauer , Ronghua Zhu
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/8611 , H01L29/063 , H01L29/0653 , H01L29/1045 , H01L29/1083 , H01L29/7835
摘要： Methods and apparatus are provided for reducing substrate leakage current of RESURF LDMOSFET devices. A semiconductor device comprises a semiconductor substrate (22) of a first type; first and second terminals (39,63) laterally spaced-apart on a surface (35) above the substrate; a first semiconductor region (32) of the first type overlying the substrate and ohmically coupled to the first terminal (39); a second semiconductor region (48) of a second opposite type in proximity to the first region and ohmically coupled to the first terminal; a third semiconductor region (30) of the second type overlying the substrate and ohmically coupled to the second terminal (63) and laterally arranged with respect to the first region; a parasitic vertical device comprising the first region and the substrate, the parasitic vertical device for permitting leakage current to flow from the first terminal to the substrate; a fourth semiconductor region (62) of the first type in proximity to the third region and ohmically coupled to the second terminal, thereby forming in combination with the third region a shorted base-collector region of a lateral transistor extending between the first and second terminals to provide diode action; a channel region (27) of the first type separating the first and third regions at the surface; a gate insulator (43) overlying the channel region; and a gate electrode (42) overlying the gate insulator.
摘要翻译：提供了减少RESURF LDMOSFET器件的衬底漏电流的方法和装置。半导体器件包括第一类型的半导体衬底（22）在衬底上方的表面（35）上横向间隔开的第一和第二端子（39,63）第一类型的第一半导体区域（32），覆盖衬底并欧姆耦合到第一端子（39）; 邻近第一区域的第二相对类型的第二半导体区域（48），并且欧姆耦合到第一端子; 第二类型的第三半导体区域（30），覆盖在所述衬底上并且欧姆耦合到所述第二端子（63）并且相对于所述第一区域横向布置; 包括第一区域和衬底的寄生垂直器件，用于允许漏电流从第一端子流到衬底的寄生垂直器件; 第一类型的第四半导体区域（62），邻近第三区域并且欧姆耦合到第二端子，从而与第三区域组合形成在第一和第二端子之间延伸的横向晶体管的短路基极集电极区域提供二极管动作; 所述第一类型的沟道区域（27）在所述表面处分隔所述第一和第三区域; 栅极绝缘体（43），覆盖所述沟道区域; 以及覆盖栅极绝缘体的栅电极（42）。

9. 发明申请

US20050242371A1 High current MOS device with avalanche protection and method of operation 审中-公开
标题翻译：大电流MOS器件具有雪崩保护和操作方法
公开(公告)号：US20050242371A1
公开(公告)日：2005-11-03
申请号：US10836730
申请日：2004-04-30
申请人： Vishnu Khemka , Amitava Bose , Vijay Parthasarathy , Ronghua Zhu
发明人： Vishnu Khemka , Amitava Bose , Vijay Parthasarathy , Ronghua Zhu
IPC分类号： H01L27/07 , H01L29/08 , H01L29/423 , H01L29/78 , H01L31/113
CPC分类号： H01L29/0847 , H01L27/0722 , H01L29/42368 , H01L29/7835
摘要： Particularly in high current applications, impact ionization induced electron-hole pairs are generated in the drain of an MOS transistor that can cause a parasitic bipolar transistor to become destructively conductive. The holes pass through the body region of the MOS transistor, which has intrinsic resistance, to the source, which is typically held at a relatively low voltage, such as ground. The hole current causes a voltage to develop in the body region, which acts as the base. This increased base voltage is what can cause the parasitic bipolar transistor to become conductive. The likelihood of this is greatly reduced by developing a voltage between the source, which acts as the emitter, and the body region by passing the channel current through an impedance between the source and the body region. This causes the emitter voltage to increase as the base voltage is increased and thereby prevent the parasitic bipolar transistor from becoming conductive.
摘要翻译：特别是在高电流应用中，在MOS晶体管的漏极中产生电子 - 电子碰撞的碰撞对，这可使寄生双极晶体管变得具有破坏性的导电性。这些孔通过具有固有电阻的MOS晶体管的体区通向保持在较低电压（例如地）的源极。空穴电流导致在作为基底的身体区域中产生电压。这种增加的基极电压可以导致寄生双极晶体管导通。通过使通道电流通过源极和体区之间的阻抗，在作为发射极的源与体区之间形成电压，大大降低了这种可能性。这导致发射极电压随着基极电压的增加而增加，从而防止寄生双极晶体管导通。

10. 发明授权

US07309638B2 Method of manufacturing a semiconductor component 有权
标题翻译：制造半导体部件的方法
公开(公告)号：US07309638B2
公开(公告)日：2007-12-18
申请号：US11182597
申请日：2005-07-14
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L21/20 , H01L21/00
CPC分类号： H01L29/866 , H01L27/0255 , H01L27/0814 , Y10S438/983
摘要： A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.
摘要翻译：半导体部件包括第一半导体区域（110,310），第一半导体区域上方的第二半导体区域（120,320），第二半导体区域上方的第三半导体区域（130,330），第四半导体区域（140,320），340），在所述第二半导体区域上方并且与所述第四半导体区域至少部分邻接的第五半导体区域（150,350），在所述第三半导体区域上方的第六半导体区域（160,360），并且电气短路到所述第五半导体区域半导体区域，以及位于第四半导体区域和第五半导体区域上方的电绝缘层（180,380）。在第四半导体区域和第五半导体区域之间的结（145,345）形成仅位于电绝缘层下方的齐纳二极管结。在一个实施例中，第七半导体区域（170）围绕第三，第四，第五和第六半导体区域。

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