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1. 发明授权

US07320094B2 Retraining derived clock receivers 有权
标题翻译：再培训派生的时钟接收器
公开(公告)号：US07320094B2
公开(公告)日：2008-01-15
申请号：US10623605
申请日：2003-07-22
申请人： Victor W. Lee , Phanindra K. Mannava , Akhilesh Kumar , Sanjay Dabral
发明人： Victor W. Lee , Phanindra K. Mannava , Akhilesh Kumar , Sanjay Dabral
IPC分类号： H04L7/00
CPC分类号： H04L1/0061 , H04J2203/0089 , H04L1/0072 , H04L25/4906 , H04L2001/0094
摘要： Systems and methods of retraining a receiver provide for determining a minimum transition density for a derived clock data link to the receiver. A retraining flit is generated based on the minimum transition density. In one approach, the retraining flit is generated by defining control data and payload data for the retraining flit. Error detection data is determined for the retraining flit based on the control and the payload data. The control data, the payload data and the error detection data have sufficient transitions to meet the minimum transition density.
摘要翻译：重新接收接收机的系统和方法提供用于确定到接收机的导出时钟数据链路的最小转换密度。基于最小过渡密度产生再培训。在一种方法中，通过为再训练飞行定义控制数据和有效载荷数据来产生再训练飞行。基于控制和有效载荷数据确定重新训练飞行的错误检测数据。控制数据，有效载荷数据和误差检测数据具有足够的过渡以满足最小转换密度。

2. 发明授权

US07328368B2 Dynamic interconnect width reduction to improve interconnect availability 有权
标题翻译：动态互连宽度减少，以提高互连可用性
公开(公告)号：US07328368B2
公开(公告)日：2008-02-05
申请号：US10801448
申请日：2004-03-12
申请人： Phanindra K. Mannava , Victor W. Lee , Akhilesh Kumar , Doddaballapur N. Jayasimha , Ioannis T. Schoinas
发明人： Phanindra K. Mannava , Victor W. Lee , Akhilesh Kumar , Doddaballapur N. Jayasimha , Ioannis T. Schoinas
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0745 , G06F11/1443 , G06F11/2007 , G06F2213/0038 , H04L1/1867 , H04L2001/0094
摘要： In some embodiments an apparatus includes a transmission error detector to detect an error of a transmission of an interconnect and a transmitting agent to retry the transmission in response to the detected error. The apparatus also includes a hard failure detector to detect a hard failure of the interconnect if the retry is unsuccessful, and a transmission width reducer to reduce a transmission width of the interconnect in response to the hard failure detector. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，一种装置包括传输错误检测器，用于响应于检测到的错误来检测互连的传输错误和发送代理重试传输。如果重试不成功，该装置还包括硬故障检测器，用于检测互连的硬故障;以及传输宽度减小器，以响应于硬故障检测器来减小互连的传输宽度。描述和要求保护其他实施例。

3. 发明授权

US07610500B2 Link power saving state 有权
标题翻译：链路省电状态
公开(公告)号：US07610500B2
公开(公告)日：2009-10-27
申请号：US11950292
申请日：2007-12-04
申请人： Naveen Cherukuri , Jeffrey R. Wilcox , Sanjay Dabral , Phanindra K. Mannava , Aaron T. Spink , David S. Dunning , Tim Frodsham , Theodore Z. Schoenborn
发明人： Naveen Cherukuri , Jeffrey R. Wilcox , Sanjay Dabral , Phanindra K. Mannava , Aaron T. Spink , David S. Dunning , Tim Frodsham , Theodore Z. Schoenborn
IPC分类号： G06F1/00 , H04B1/38 , H04L27/00 , H04L1/00
CPC分类号： G06F1/3209 , G06F1/3253 , H04L12/12 , Y02D10/151 , Y02D50/20 , Y02D50/40
摘要： Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.
摘要翻译：公开了用于点对点链路的低功率状态的方法，装置和系统的实施例。在低功率状态期间，差分发送对的两个导体上的信号被驱动到电气空闲。模拟活动检测器在低功率状态期间被使能，并且在正常功率状态期间被禁用。退出低功耗状态不需要物理层重新初始化的顺序。还描述和要求保护其他实施例。

4. 发明授权

US07313712B2 Link power saving state 有权
标题翻译：链路省电状态
公开(公告)号：US07313712B2
公开(公告)日：2007-12-25
申请号：US10850733
申请日：2004-05-21
申请人： Naveen Cherukuri , Jeffrey R. Wilcox , Sanjay Dabral , Phanindra K. Mannava , Aaron T. Spink , David S. Dunning , Tim Frodsham , Theodore Z. Schoenborn
发明人： Naveen Cherukuri , Jeffrey R. Wilcox , Sanjay Dabral , Phanindra K. Mannava , Aaron T. Spink , David S. Dunning , Tim Frodsham , Theodore Z. Schoenborn
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3209 , G06F1/3253 , H04L12/12 , Y02D10/151 , Y02D50/20 , Y02D50/40
摘要： Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.
摘要翻译：公开了用于点对点链路的低功率状态的方法，装置和系统的实施例。在低功率状态期间，差分发送对的两个导体上的信号被驱动到电气空闲。模拟活动检测器在低功率状态期间被使能，并且在正常功率状态期间被禁用。退出低功耗状态不需要物理层重新初始化的顺序。还描述和要求保护其他实施例。

5. 发明申请

US20090265472A1 Method, System, and Apparatus for System Level Initialization 有权
标题翻译：用于系统级初始化的方法，系统和装置
公开(公告)号：US20090265472A1
公开(公告)日：2009-10-22
申请号：US12348723
申请日：2009-01-05
申请人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddabaliapur Narasimha-Murthy Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava , Ioannis T. Schoinas
发明人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddabaliapur Narasimha-Murthy Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava , Ioannis T. Schoinas
IPC分类号： G06F15/16 , G06F15/177
CPC分类号： H04L67/125 , H04L69/324
摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated.For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
摘要翻译：讨论了用于系统和组件在点对点架构中的多个初始化技术。因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。

6. 发明授权

US07991875B2 Link level retry scheme 有权
标题翻译：链路级重试方案
公开(公告)号：US07991875B2
公开(公告)日：2011-08-02
申请号：US11326982
申请日：2006-01-06
申请人： Ching-Tsun Chou , Suresh Chittor , Andalib Khan , Akhilesh Kumar , Phanindra K. Mannava , Rajee S. Ram , Sujoy Sen , Srinand Venkatesan , Kiran Padwekar
发明人： Ching-Tsun Chou , Suresh Chittor , Andalib Khan , Akhilesh Kumar , Phanindra K. Mannava , Rajee S. Ram , Sujoy Sen , Srinand Venkatesan , Kiran Padwekar
IPC分类号： G06F15/173 , G06F15/16 , G06F11/00 , G01R31/08 , H04L1/00 , H04L12/56 , H04L12/28 , H04L1/18 , H04J3/24
CPC分类号： H04L1/188 , H04L1/1614 , H04L1/1671 , H04L1/1874 , H04L29/06 , H04L69/324 , H04L2001/125
摘要： A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.
摘要翻译：提供了一个链路层系统。链路层系统是第一链路层控制模块和用于存储传输的数据分组的重试队列。重试控制模块耦合到第一链路层控制模块，当第一链路层控制模块接收到确认位时，引导重试队列丢弃所发送的数据分组。

7. 发明授权

US07738484B2 Method, system, and apparatus for system level initialization 有权
标题翻译：用于系统级初始化的方法，系统和装置
公开(公告)号：US07738484B2
公开(公告)日：2010-06-15
申请号：US11011801
申请日：2004-12-13
申请人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddaballapur N. Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava
发明人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddaballapur N. Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava
IPC分类号： H04L12/42
CPC分类号： H04L67/125 , H04L69/324
摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated.For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
摘要翻译：讨论了用于系统和组件在点对点架构中的多个初始化技术。因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。

8. 发明授权

US08606934B2 Method, system, and apparatus for system level initialization by conveying capabilities and identifiers of components 有权
标题翻译：通过传送组件的功能和标识符来进行系统级初始化的方法，系统和装置
公开(公告)号：US08606934B2
公开(公告)日：2013-12-10
申请号：US12348723
申请日：2009-01-05
申请人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddabaliapur Narasimha-Murthy Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava , Ioannis T. Schoinas
发明人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddabaliapur Narasimha-Murthy Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava , Ioannis T. Schoinas
IPC分类号： G06F3/00 , G06F13/00 , G06F15/16 , G06F15/177 , H04L12/42
CPC分类号： H04L67/125 , H04L69/324
摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated.For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
摘要翻译：讨论了用于系统和组件在点对点架构中的多个初始化技术。因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。

9. 发明授权

US07016304B2 Link level retry scheme 失效
公开(公告)号：US07016304B2
公开(公告)日：2006-03-21
申请号：US09861260
申请日：2001-05-18
申请人： Ching-Tsun Chou , Suresh Chittor , Andalib Khan , Akhilesh Kumar , Phanindra K. Mannava , Rajee S. Ram , Sujoy Sen , Srinand Venkatesan , Kiran Padwekar
发明人： Ching-Tsun Chou , Suresh Chittor , Andalib Khan , Akhilesh Kumar , Phanindra K. Mannava , Rajee S. Ram , Sujoy Sen , Srinand Venkatesan , Kiran Padwekar
IPC分类号： G01R31/08
CPC分类号： H04L1/188 , H04L1/1614 , H04L1/1671 , H04L1/1874 , H04L29/06 , H04L69/324 , H04L2001/125
摘要： A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.

10. 发明申请

US20090055555A1 METHOD AND SYSTEM FOR FLEXIBLE AND NEGOTIABLE EXCHANGE OF LINK LAYER FUNCTIONAL PARAMETERS 审中-公开
公开(公告)号：US20090055555A1
公开(公告)日：2009-02-26
申请号：US12242283
申请日：2008-09-30
申请人： Phanindra K. Mannava , Victor W. Lee , Aaron T. Spink
发明人： Phanindra K. Mannava , Victor W. Lee , Aaron T. Spink
IPC分类号： G06F3/00
CPC分类号： G06F13/423
摘要： A proposal is discussed that facilitates exchanging parameters for a link layer that allows a variable number of parameters without changing a communication protocol. Likewise, the proposal allows for both components connected via the link to negotiate values for the parameters that are exchanged without a need for external agent intervention or redundancy.

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