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1. 发明授权

US08969969B2 High threshold voltage NMOS transistors for low power IC technology 有权
公开(公告)号：US08969969B2
公开(公告)日：2015-03-03
申请号：US12727312
申请日：2010-03-19
申请人： Victor W. C. Chan , Narasimhulu Kanike , Huiling Shang , Varadarajan Vidya , Jun Yuan , Roger Allen Booth, Jr.
发明人： Victor W. C. Chan , Narasimhulu Kanike , Huiling Shang , Varadarajan Vidya , Jun Yuan , Roger Allen Booth, Jr.
IPC分类号： H01L27/092 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823412
摘要： Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.

2. 发明授权

US07193254B2 Structure and method of applying stresses to PFET and NFET transistor channels for improved performance 有权
标题翻译：对PFET和NFET晶体管通道施加应力的结构和方法，以提高性能
公开(公告)号：US07193254B2
公开(公告)日：2007-03-20
申请号：US10904808
申请日：2004-11-30
申请人： Victor W. C. Chan , Yong M. Lee , Haining Yang
发明人： Victor W. C. Chan , Yong M. Lee , Haining Yang
IPC分类号： H01L29/80
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/665
摘要： A semiconductor device structure is provided which includes a first semiconductor device; a second semiconductor device; and a unitary stressed film disposed over both the first and second semiconductor devices. The stressed film has a first portion overlying the first semiconductor device, the first portion imparting a first magnitude compressive stress to a conduction channel of the first semiconductor device, the stressed film further having a second portion overlying the second semiconductor device, the second portion not imparting the first magnitude compressive stress to a conduction channel of the second semiconductor device, the second portion including an ion concentration not present in the second portion such that the second portion imparts one of a compressive stress having a magnitude much lower than the first magnitude, zero stress, and a tensile stress to the conduction channel of the second semiconductor device.
摘要翻译：提供一种半导体器件结构，其包括第一半导体器件; 第二半导体器件; 以及设置在第一和第二半导体器件两者上的单一应力膜。应力膜具有覆盖第一半导体器件的第一部分，第一部分向第一半导体器件的导电通道施加第一大小的压缩应力，应力膜还具有覆盖第二半导体器件的第二部分，第二部分不将第一强度压缩应力施加到第二半导体器件的导电通道，第二部分包括不存在于第二部分中的离子浓度，使得第二部分施加具有远低于第一大小的量级的压缩应力之一，零应力和对第二半导体器件的导电通道的拉伸应力。

3. 发明授权

US07473593B2 Semiconductor transistors with expanded top portions of gates 有权
标题翻译：半导体晶体管具有扩大的栅极顶部
公开(公告)号：US07473593B2
公开(公告)日：2009-01-06
申请号：US11275514
申请日：2006-01-11
申请人： Brent Alan Anderson , Victor W. C. Chan , Edward Joseph Nowak
发明人： Brent Alan Anderson , Victor W. C. Chan , Edward Joseph Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L29/1083 , H01L29/42376 , H01L29/66507 , H01L29/6659 , H01L29/66772 , H01L29/66795 , H01L29/785 , H01L29/78654
摘要： A method for forming a semiconductor transistor with an expanded top portion of a gate The gate is expanded through implanting atoms in the top portion of transistor's gate electrode region. The transistor formed includes a semiconductor region having two source/drain regions and a gate dielectric region formed on the channel region between the source/drain regions. The gate electrode region is formed on the gate dielectric region. The gate electrode region is formed such that it is electrically insulated from the channel region by the gate dielectric region. The top of the gate electrode region formed is wider than the bottom of the gate electrode region.
摘要翻译：用于形成具有扩大的栅极顶部的半导体晶体管的方法通过在晶体管的栅电极区域的顶部中注入原子来扩展栅极。所形成的晶体管包括具有两个源极/漏极区域和形成在源极/漏极区域之间的沟道区域上的栅极电介质区域的半导体区域。栅极区域形成在栅极电介质区域上。栅电极区域形成为通过栅极电介质区域与沟道区域电绝缘。所形成的栅极电极区域的顶部比栅电极区域的底部宽。

4. 发明申请

US20080246056A1 SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET 审中-公开
标题翻译：使用间隔层叠层的硅化物形成和硅氧烷沟道界面及相关PFET
公开(公告)号：US20080246056A1
公开(公告)日：2008-10-09
申请号：US11697806
申请日：2007-04-09
申请人： Victor W. C. Chan , Thomas W. Dyer , Sunfei Fang , Jinghong Li , Teck J. Tang , Henry K. Utomo , Jiang Yan
发明人： Victor W. C. Chan , Thomas W. Dyer , Sunfei Fang , Jinghong Li , Teck J. Tang , Henry K. Utomo , Jiang Yan
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823864 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/7843
摘要： Methods of forming a suicide in an embedded silicon germanium (eSiGe) source/drain region using a suicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and a related PFET with an eSiGe source/drain region and a compressive stress liner in close proximity to a silicon channel thereof, are disclosed. In one embodiment, a method includes providing a gate having a nitrogen-containing spacer adjacent thereto and an epitaxially grown silicon germanium (eSiGe) region adjacent to a silicon channel of the gate; removing the nitrogen-containing spacer that does not extend over the interface between the eSiGe source/drain region and the silicon channel; forming a single silicide prevention spacer about the gate, the single silicide prevention spacer overlapping the interface; and forming the silicide in the eSiGe source/drain region using the single silicide prevention spacer to prevent the silicide from forming in at least an extension area of the silicon channel.
摘要翻译：在嵌入式硅锗（eSiGe）源极/漏极区域中使用与eSiGe和硅沟道之间的界面重叠的防止硅化物的衬垫形成硅化物的方法以及具有eSiGe源极/漏极区域和压应力衬垫的相关PFET 公开了其接近硅通道的方式。在一个实施例中，一种方法包括提供具有与其相邻的含氮隔离物的栅极和与栅极的硅沟道相邻的外延生长的硅锗（eSiGe）区域; 去除不在eSiGe源极/漏极区域和硅沟道之间的界面上延伸的含氮隔离物; 在栅极周围形成单个硅化物防止间隔物，单个硅化物防止间隔物与界面重叠; 以及使用单个硅化物防止间隔物在eSiGe源极/漏极区域中形成硅化物，以防止硅化物在硅沟道的至少延伸区域中形成。

5. 发明授权

US07482216B2 Substrate engineering for optimum CMOS device performance 失效
标题翻译：基板工程，实现最佳的CMOS器件性能
公开(公告)号：US07482216B2
公开(公告)日：2009-01-27
申请号：US11474774
申请日：2006-06-26
申请人： Victor W. C. Chan , Meikei Ieong , Min Yang
发明人： Victor W. C. Chan , Meikei Ieong , Min Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807
摘要： An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a direction and the at least one NFET has a current flow in a direction. The direction is perpendicular to the direction. A method of fabricating such as integrated semiconductor structure is also provided.
摘要翻译：提供了位于半导体衬底顶部的具有不同类型的互补金属氧化物半导体器件（CMOS）即PFET和NFET的集成半导体结构，其中每个CMOS器件被制造成使得每个器件的电流是最佳的。具体地，该结构包括具有（110）表面取向的半导体衬底和指向电流<001>方向的凹口; 以及位于半导体衬底上的至少一个PFET和至少一个NFET。所述至少一个PFET具有沿<110>方向的电流，并且所述至少一个NFET具有沿<100>方向的电流。 <110>方向垂直于<100>方向。还提供了诸如集成半导体结构的制造方法。

6. 发明授权

US07442611B2 Method of applying stresses to PFET and NFET transistor channels for improved performance 有权
标题翻译：向PFET和NFET晶体管通道施加应力以提高性能的方法
公开(公告)号：US07442611B2
公开(公告)日：2008-10-28
申请号：US11657154
申请日：2007-01-24
申请人： Victor W. C. Chan , Yong M. Lee , Haining Yang
发明人： Victor W. C. Chan , Yong M. Lee , Haining Yang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/665
摘要： A method is provided for fabricating a semiconductor device structure. In such method a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), each of the NFET and the PFET having a conduction channel disposed in a single-crystal semiconductor region of a substrate. A stressed film having a compressive stress at a first magnitude can be formed to overlie the PFET and the NFET. Desirably, a mask is formed to cover the PFET while exposing the NFET, after which, desirably, a portion of the stressed film overlying the NFET is subjected to ion implantation, while the mask protects another portion of the stressed film overlying the PFET from the ion implantation. The substrate can then be annealed, whereby, desirably, the compressive stress of the implanted portion of the stressed film is much reduced from the first magnitude by the annealing. In such way, the implanted portion of the stressed film overlying the NFET desirably imparts one of a much reduced magnitude compressive stress, a zero stress and a tensile stress to the conduction channel of the NFET. Another portion of the stressed film can continue to impart the compressive stress at the first magnitude to the conduction channel of the PFET.
摘要翻译：提供了制造半导体器件结构的方法。在这种方法中，p型场效应晶体管（PFET）和n型场效应晶体管（NFET），NFET和PFET中的每一个具有设置在基板的单晶半导体区域中的导电沟道。可以形成具有第一大小的压应力的应力膜覆盖在PFET和NFET上。期望地，形成掩模以在暴露NFET的同时覆盖PFET，之后理想地，覆盖NFET的应力膜的一部分经受离子注入，而掩模保护覆盖PFET的应力膜的另一部分与离子注入。然后可以对衬底进行退火，因此期望地，应力膜的注入部分的压缩应力通过退火从第一量级大大降低。以这种方式，覆盖NFET的应力膜的注入部分期望地将大大减小的压缩应力，零应力和拉伸应力中的一个施加到NFET的传导通道。应力膜的另一部分可以继续将第一大小的压应力赋予PFET的传导通道。

7. 发明授权

US08466503B2 Semiconductor transistors with expanded top portions of gates 失效
标题翻译：半导体晶体管具有扩大的栅极顶部
公开(公告)号：US08466503B2
公开(公告)日：2013-06-18
申请号：US12189298
申请日：2008-08-11
申请人： Brent Alan Anderson , Victor W. C. Chan , Edward Joseph Nowak
发明人： Brent Alan Anderson , Victor W. C. Chan , Edward Joseph Nowak
IPC分类号： H01L29/76
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L29/1083 , H01L29/42376 , H01L29/66507 , H01L29/6659 , H01L29/66772 , H01L29/66795 , H01L29/785 , H01L29/78654
摘要： A semiconductor transistor with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor with an expanded top portion of a gate includes (a) a semiconductor region which includes a channel region and first and second source/drain regions; the channel region is disposed between the first and second source/drain regions, (b) a gate dielectric region in direct physical contact with the channel region, and (c) a gate electrode region which includes a top portion and a bottom portion. The bottom portion is in direct physical contact with the gate dielectric region. A first width of the top portion is greater than a second width of the bottom portion. The gate electrode region is electrically insulated from the channel region by the gate dielectric region.
摘要翻译：具有扩大的栅极顶部的半导体晶体管及其形成方法。具有扩大的栅极顶部的半导体晶体管包括：（a）包括沟道区和第一和第二源极/漏极区的半导体区; 沟道区域设置在第一和第二源极/漏极区域之间，（b）与沟道区域直接物理接触的栅极电介质区域，以及（c）包括顶部和底部的栅电极区域。底部部分与栅极电介质区域直接物理接触。顶部的第一宽度大于底部的第二宽度。栅电极区域通过栅极电介质区域与沟道区域电绝缘。

8. 发明授权

US07148559B2 Substrate engineering for optimum CMOS device performance 有权
公开(公告)号：US07148559B2
公开(公告)日：2006-12-12
申请号：US10604003
申请日：2003-06-20
申请人： Victor W. C. Chan , Meikei Leong , Min Yang
发明人： Victor W. C. Chan , Meikei Leong , Min Yang
IPC分类号： H01L27/76 , H01L21/8238
CPC分类号： H01L21/823807
摘要： An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a direction and the at least one NFET has a current flow in a direction. The direction is perpendicular to the direction. A method of fabricating such as integrated semiconductor structure is also provided.

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