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1. 发明申请

WO2011053880A2 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2011053880A2
公开(公告)日：2011-05-05
申请号：PCT/US2010/054877
申请日：2010-10-29
申请人： VISHAY-SILICONIX , PATTANAYAK, Deva , OWYANG, King , KASEM, Mohammed , TERRILL, Kyle , KATRARO, Reuven , CHEN, Kuo-In , CHOI, Calvin , CHEN, Qufei , LUI, Kam Hong , XU, Robert , WONG, Ronald
发明人： PATTANAYAK, Deva , OWYANG, King , KASEM, Mohammed , TERRILL, Kyle , KATRARO, Reuven , CHEN, Kuo-In , CHOI, Calvin , CHEN, Qufei , LUI, Kam Hong , XU, Robert , WONG, Ronald
IPC分类号： H01L21/60 , H01L21/28
CPC分类号： H01L29/7809 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L29/408 , H01L29/41766 , H01L29/45 , H01L29/456 , H01L29/66734 , H01L29/7813 , H01L2224/0401 , H01L2224/05 , H01L2224/05552 , H01L2224/05554 , H01L2224/06051 , H01L2224/13007 , H01L2224/13014 , H01L2224/13023 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.
摘要翻译：半导体器件（例如，倒装芯片）包括通过中间层与漏极接触分离的衬底层。通过中间层的沟槽状馈通元件用于在器件工作时电连接漏极接触和衬底层。

2. 发明申请

WO2011031563A2 SUPER JUNCTION TRENCH POWER MOSFET DEVICES 审中-公开
标题翻译：超级结型沟槽功率MOSFET器件
公开(公告)号：WO2011031563A2
公开(公告)日：2011-03-17
申请号：PCT/US2010/047039
申请日：2010-08-27
申请人： VISHAY-SILICONIX , GAO, Yang , TERRILL, Kyle , PATTANAYAK, Deva , CHEN, Kuo-In , CHAU, The-Tu , SHI, Sharon , CHEN, Qufei
发明人： GAO, Yang , TERRILL, Kyle , PATTANAYAK, Deva , CHEN, Kuo-In , CHAU, The-Tu , SHI, Sharon , CHEN, Qufei
IPC分类号： H01L29/78 , H01L21/336 , H01L29/812
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： In a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device, a column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.
摘要翻译：在超级结沟槽功率MOSFET（金属氧化物半导体场效应晶体管）器件中，超级结中的一列p型掺杂剂与第一列n型掺杂剂分开第一通过第二列氧化物从第二列n型掺杂剂中除去。在n沟道器件中，用于FET的栅极元件有利地位于p型掺杂剂列的上方; 并且在p沟道器件中，用于FET的栅极元件有利地位于n型掺杂剂的列上方。

3. 发明申请

WO2011031565A2 SUPER JUNCTION TRENCH POWER MOSFET DEVICE FABRICATION 审中-公开
标题翻译：超级结型沟槽功率MOSFET器件的制造
公开(公告)号：WO2011031565A2
公开(公告)日：2011-03-17
申请号：PCT/US2010/047046
申请日：2010-08-27
申请人： VISHAY-SILICONIX , GAO, Yang , TERRILL, Kyle , PATTANAYAK, Deva , CHEN, Kuo-In , CHAU, The-Tu , SHI, Sharon , CHEN, Qufei
发明人： GAO, Yang , TERRILL, Kyle , PATTANAYAK, Deva , CHEN, Kuo-In , CHAU, The-Tu , SHI, Sharon , CHEN, Qufei
IPC分类号： H01L29/78 , H01L21/336 , H01L29/812
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： Methods of fabricating a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device are described. A column of p- type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.
摘要翻译：描述制造超级结沟槽功率MOSFET（金属氧化物半导体场效应晶体管）器件的方法。超级结中的p型掺杂剂列通过第一列氧化物与第一列n型掺杂剂分离，并且通过第二列氧化物从第二列n型掺杂剂分离。在n沟道器件中，用于FET的栅极元件有利地位于p型掺杂剂列的上方; 并且在p沟道器件中，用于FET的栅极元件有利地位于n型掺杂剂的列上方。

4. 发明申请

WO2007092089A1 TRENCH POLYSILICON DIODE 审中-公开
公开(公告)号：WO2007092089A1
公开(公告)日：2007-08-16
申请号：PCT/US2006/049132
申请日：2006-12-22
申请人： VISHAY-SILICONIX , CHEN, Qufei , XU, Robert , TERRILL, Kyle , PATTANAYAK, Deva
发明人： CHEN, Qufei , XU, Robert , TERRILL, Kyle , PATTANAYAK, Deva
IPC分类号： H01L29/861 , H01L29/866 , H01L27/04
CPC分类号： H01L29/7813 , H01L27/0255 , H01L27/0629 , H01L27/0814 , H01L29/66727 , H01L29/66734 , H01L29/7808 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention include a method of manufacturing a trench polysilicon diode. The method includes forming a N- (P-) type epitaxial region on a N+ (P+) type substrate and forming a trench in the N- (P-) type epitaxial region. The method further includes forming a insulating layer in the trench and filling the trench with polysilicon forming a top surface of the trench. The method further includes forming P+ (N+) type doped polysilicon region and N+ (P+) type doped polysilicon region in the trench and forming a diode in the trench wherein a portion of the diode is lower than the top surface of the trench.
摘要翻译：本发明的实施例包括制造沟槽多晶硅二极管的方法。该方法包括在N +（P +）型衬底上形成N-（P-）型外延区，并在N-（P-）型外延区中形成沟槽。该方法还包括在沟槽中形成绝缘层，并用形成沟槽顶表面的多晶硅填充沟槽。该方法还包括在沟槽中形成P +（N +）型掺杂多晶硅区域和N +（P +）型掺杂多晶硅区域，并在沟槽中形成二极管，其中二极管的一部分低于沟槽的顶表面。

5. 发明申请

WO2006126998A1 TRENCH METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR 审中-公开
标题翻译： TRENCH金属氧化物半导体场效应晶体管
公开(公告)号：WO2006126998A1
公开(公告)日：2006-11-30
申请号：PCT/US2005/018096
申请日：2005-05-24
申请人： VISHAY-SILICONIX , PATTANAYAK, Deva , QI, Jason, Jianhai , BAI, Yuming , LUI, Kam-Hong , WONG, Ronald
发明人： PATTANAYAK, Deva , QI, Jason, Jianhai , BAI, Yuming , LUI, Kam-Hong , WONG, Ronald
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/407 , H01L29/1095 , H01L29/41766 , H01L29/66734 , H01L29/781
摘要： Embodiments here described provide a striped or closed cell trench metal-oxide semiconductor field effect transistor (TMOSFET). The striped or closed cell TMOSFET comprises a source region, a body region disposed above the source region, a drift region disposed above the body region, a drain region disposed above the drift region. A gate region is disposed above the source region and adjacent the body region. A gate insulator region electrically isolates the gate region from the source region, body region, drift region and drain region. The body region is electrically coupled to the source region.
摘要翻译：这里描述的实施例提供了一种带状或闭孔的沟槽金属氧化物半导体场效应晶体管（TMOSFET）。条状或闭孔TMOSFET包括源极区域，设置在源极区域上方的体区域，设置在身体区域上方的漂移区域，设置在漂移区域上方的漏极区域。栅极区域设置在源极区域的上方并与身体区域相邻。栅极绝缘体区域将栅极区域与源极区域，体区域，漂移区域和漏极区域电隔离。身体区域电耦合到源区域。

6. 发明申请

WO2007076063A3 HIGH MOBILITY POWER METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTORS 审中-公开
公开(公告)号：WO2007076063A3
公开(公告)日：2007-07-05
申请号：PCT/US2006/049133
申请日：2006-12-22
申请人： VISHAY-SILICONIX , PATTANAYAK, Deva , CHEN, Kuo-In , CHAU, The-Tu
发明人： PATTANAYAK, Deva , CHEN, Kuo-In , CHAU, The-Tu
IPC分类号： H01L29/778
摘要： High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total "on" resistance of the device.

7. 发明申请

WO2007100803A1 PROCESS FOR FORMING A SHORT CHANNEL TRENCH MOSFET AND DEVICE 审中-公开
标题翻译：用于形成短路通道MOSFET和器件的方法
公开(公告)号：WO2007100803A1
公开(公告)日：2007-09-07
申请号：PCT/US2007/005033
申请日：2007-02-23
申请人： PATTANAYAK, Deva , LEE, Zachary
发明人： PATTANAYAK, Deva , LEE, Zachary
IPC分类号： H01L21/336 , H01L21/76 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/26513 , H01L21/26586 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/66734
摘要： A process for forming a short channel trench MOSFET. The process can include forming a first implant at the bottom of a trench that is formed in the body of the trench MOSFET and forming a second or angled implant that is tilted in its orientation and directed perpendicular to the trench that is formed in the body of the trench MOSFET. The second implant can be adjusted so that it does not reach the bottom of the trench. In one embodiment the angled implant can be an n-type material.
摘要翻译：用于形成短通道沟槽MOSFET的工艺。该工艺可以包括在形成在沟槽MOSFET的主体中的沟槽的底部形成第一注入，并且形成第二或成角度的注入件，其倾斜于其取向并垂直于形成在沟槽MOSFET的主体中的沟槽沟槽MOSFET。可以调节第二植入物，使其不到达沟槽的底部。在一个实施例中，成角度的植入物可以是n型材料。

8. 发明申请

WO2015199949A1 MODULATED SUPER JUNCTION POWER MOSFET DEVICES 审中-公开
标题翻译：调制超级功率MOSFET器件
公开(公告)号：WO2015199949A1
公开(公告)日：2015-12-30
申请号：PCT/US2015/034480
申请日：2015-06-05
申请人： VISHAY-SILICONIX
发明人： PATTANAYAK, Deva , TORNBLAD, Olof
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/7802
摘要： A semiconductor device - e.g., a super junction power MOSFET - includes a number of columns of one type of dopant formed in a region of another type of dopant. Generally speaking, the columns are modulated in some manner. For example, the widths (e.g., diameters) of some columns are greater than the widths of other columns.
摘要翻译：半导体器件（例如超结功率MOSFET）包括在另一种掺杂剂的区域中形成的一种类型的掺杂剂的列。一般来说，列以某种方式进行调制。例如，一些列的宽度（例如，直径）大于其他列的宽度。

9. 发明申请

WO2015195372A1 PROCESSES USED IN FABRICATING A METAL-INSULATOR-SEMICONDUCTOR FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：用于制造金属绝缘体半导体场效应晶体管的工艺
公开(公告)号：WO2015195372A1
公开(公告)日：2015-12-23
申请号：PCT/US2015/034465
申请日：2015-06-05
申请人： VISHAY-SILICONIX
发明人： TIPIRNENI, Naveen , PATTANAYAK, Deva
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/8234 , H01L29/0619 , H01L29/402 , H01L29/41766 , H01L29/66719 , H01L29/66727 , H01L29/7811 , H01L29/7823
摘要： During fabrication, a second oxide layer is disposed over a first region and a second region of a structure. The second region includes a first oxide layer between the second oxide layer and an epitaxial layer. The first region corresponds to an active region of a metal-insulator-semiconductor field effect transistor (MISFET), and a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region are formed in the first region. The second region corresponds to a termination region of the MISFET. A mask is formed over the second region, and parts of the second oxide layer and the first oxide layer that are exposed through the gaps are removed, thereby exposing the epitaxial layer. Second-type dopant is deposited into the epitaxial layer through the resultant openings in the first and second oxide layers, thereby forming field rings for the MISFET.
摘要翻译：在制造期间，第二氧化物层设置在结构的第一区域和第二区域上。第二区域包括在第二氧化物层和外延层之间的第一氧化物层。第一区域对应于金属 - 绝缘体 - 半导体场效应晶体管（MISFET）的有源区，并且形成第一类型掺杂源区域，第二类型掺杂剂体区域和第二类型掺杂剂注入区域第一个地区。第二区域对应于MISFET的端接区域。在第二区域上形成掩模，并且去除通过间隙暴露的第二氧化物层和第一氧化物层的部分，从而暴露外延层。第二类掺杂剂通过第一和第二氧化物层中的所得开口沉积到外延层中，从而形成用于MISFET的场环。

10. 发明申请

WO2015199951A1 SEMICONDUCTOR DEVICE WITH COMPOSITE TRENCH AND IMPLANT COLUMNS 审中-公开
标题翻译：具有复合TRENCH和IMPLANT COLUMNS的半导体器件
公开(公告)号：WO2015199951A1
公开(公告)日：2015-12-30
申请号：PCT/US2015/034487
申请日：2015-06-05
申请人： VISHAY-SILICONIX
发明人： PATTANAYAK, Deva , AGGARWAL, Sandeep
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66712 , H01L21/2254 , H01L21/283 , H01L21/74 , H01L21/743 , H01L29/0634 , H01L29/1095 , H01L29/7802
摘要： A metal insulator semiconductor field effect transistor (MISFET) such as a super junction metal oxide semiconductor FET with high voltage breakdown is realized by, in essence, stacking a relatively low aspect ratio column (trenches filled with dopant, e.g., p-type dopant) on top of a volume or volumes formed by implanting the dopant in lower layers. Together, the low aspect ratio column and the volume(s) form a continuous high aspect ratio column.
摘要翻译：通过本质上堆叠相对较低的纵横比的列（填充有掺杂剂的沟槽，例如p型掺杂剂）来实现诸如具有高电压击穿的超结金属氧化物半导体FET的金属绝缘体半导体场效应晶体管（MISFET）在通过在下层中注入掺杂剂而形成的体积或体积之上。一起，低纵横比柱和体积形成连续的高纵横比列。

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