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1. 发明申请

US20100169401A1 FILTER FOR NETWORK INTRUSION AND VIRUS DETECTION 有权
标题翻译：用于网络入侵和病毒检测的过滤器
公开(公告)号：US20100169401A1
公开(公告)日：2010-07-01
申请号：US12346734
申请日：2008-12-30
申请人： VINODH GOPAL , Christopher F. Clark , Gilbert Wolrich , Wajdi Feghali
发明人： VINODH GOPAL , Christopher F. Clark , Gilbert Wolrich , Wajdi Feghali
IPC分类号： G06F17/10
CPC分类号： H04L63/145 , G06F7/02 , G06F17/30949 , G06F17/30985 , G06F21/567 , G06F2207/025 , H04L63/0245 , H04L63/1416
摘要： Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.
摘要翻译：公开了对网络包检测进行字符串匹配的方法和装置。在一些实施例中，存在一组字符串匹配限幅电路，该组的每个片电路被配置为与其他片电路并行地执行字符串匹配步骤。每个切片电路可以包括从输入数据蒸汽存储一些数量的数据字节的输入窗口。如果需要，可以填充数据的输入窗口，然后乘以多项式模数不可约伽罗瓦域多项式以生成散列索引。可以访问与散列索引相对应的存储器的存储位置，以产生一组H个切片命中信号的切片命中信号。切片命中信号可以被提供给AND逻辑阵列，其中H组切片命中信号的组合被逻辑地组合成匹配结果。

2. 发明申请

US20140095845A1 APPARATUS AND METHOD FOR EFFICIENTLY EXECUTING BOOLEAN FUNCTIONS 审中-公开
标题翻译：有效执行布尔函数的装置和方法
公开(公告)号：US20140095845A1
公开(公告)日：2014-04-03
申请号：US13631807
申请日：2012-09-28
申请人： Vinodh Gopal , Wajdi Feghali , Gilbert Wolrich , Kirk Yap
发明人： Vinodh Gopal , Wajdi Feghali , Gilbert Wolrich , Kirk Yap
IPC分类号： G06F9/30
摘要： An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, a processor according to one embodiment of the invention comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.
摘要翻译：描述了一种用于在流水线处理器中执行有效的布尔运算的装置和方法，其在一个实施例中不本地支持三个操作数指令。例如，根据本发明的一个实施例的处理器包括：一组用于存储打包操作数的寄存器; 用于执行单个指令的布尔运算逻辑，其使用打包在该组寄存器中的三个或更多个源操作数，布尔运算逻辑读取至少三个源操作数，并且立即值对三个源操作数执行布尔运算，其中，布尔操作包括：组合从三个操作数中的每一个读取的位以形成立即值的索引，该索引标识立即值内的位位置; 从识别的位置读取该位从立即值; 并将来自所识别的立即值的比特位置的比特存储在目的地寄存器中。

3. 发明申请

US20100153829A1 RESIDUE GENERATION 失效
标题翻译：残留生成
公开(公告)号：US20100153829A1
公开(公告)日：2010-06-17
申请号：US12336029
申请日：2008-12-16
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi Feghali
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi Feghali
IPC分类号： H03M13/09 , G06F7/72 , G06F11/10
CPC分类号： G06F7/724 , H03M13/091
摘要： In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.
摘要翻译：在一个实施例中，提供电路以至少部分地基于至少部分地基于分组产生的操作和数据流来生成残差。操作可以包括至少一个缩减操作的迭代，包括（a）将第一值与数据流的至少一部分相乘，以及（b）通过添加数据流的至少一个其他部分来产生减少是乘法的结果。所述操作可以包括至少一个其它减少操作，其包括（c）至少部分地基于所述减少，通过与另一个流的至少一部分乘以第二值来产生另一结果，（d）通过至少加入来产生第三值另一个流的另一部分到另一个结果，以及（e）至少部分地基于第三个值执行巴雷特还原来产生残留物。

4. 发明授权

US08189792B2 Method and apparatus for performing cryptographic operations 有权
标题翻译：用于执行加密操作的方法和装置
公开(公告)号：US08189792B2
公开(公告)日：2012-05-29
申请号：US12005680
申请日：2007-12-28
申请人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
发明人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
IPC分类号： G06F21/00
CPC分类号： H04L9/0631 , H04L2209/125
摘要： In one embodiment, the present invention includes a processor having logic to perform a round of a cryptographic algorithm responsive to first and second round micro-operations to perform the round on first and second pairs of columns, where the logic includes dual datapaths that are half the width of the cryptographic algorithm width (or smaller). Additional logic may be used to combine the results of the first and second round micro-operations to obtain a round result. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括处理器，其具有响应于第一和第二轮微操作执行一轮加密算法以在第一和第二列列上执行循环的逻辑，其中该逻辑包括半数的双数据通路加密算法宽度（或更小）的宽度。可以使用附加逻辑来组合第一和第二轮微操作的结果以获得圆形结果。描述和要求保护其他实施例。

5. 发明授权

US08042025B2 Determining a message residue 有权
标题翻译：确定消息残差
公开(公告)号：US08042025B2
公开(公告)日：2011-10-18
申请号：US12291621
申请日：2008-11-12
申请人： Vinodh Gopal , Gilbert Wolrich , Wajdi Feghali , Erdinc Ozturk , Shay Gueron
发明人： Vinodh Gopal , Gilbert Wolrich , Wajdi Feghali , Erdinc Ozturk , Shay Gueron
IPC分类号： H03M13/03
CPC分类号： G06F7/724 , H03M13/091
摘要： In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format, and perform a polynomial multiplication of the first number and the at least a portion of the first number.
摘要翻译：在一个方面，用于确定相对于包括一系列段的消息的多项式的模块余数的电路。在另一方面，访问具有第一末端格式的第一号码的至少一部分的电路基于具有与第一末端格式相反的端格式的第三号码的位反射和位移来确定第二号码，以及执行第一数字和第一数字的至少一部分的多项式相乘。

6. 发明申请

US20100205455A1 DIFFUSION AND CRYPTOGRAPHIC-RELATED OPERATIONS 有权
标题翻译：扩展和与CRIPTO图相关的操作
公开(公告)号：US20100205455A1
公开(公告)日：2010-08-12
申请号：US12368196
申请日：2009-02-09
申请人： Vinodh Gopal , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Robert Ottavi , Sean Gulley
发明人： Vinodh Gopal , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Robert Ottavi , Sean Gulley
IPC分类号： H04L9/00
CPC分类号： G09C1/00 , H04L9/0637 , H04L2209/12
摘要： An embodiment includes at least one processing unit to perform at least first and second sets of diffusion-related operations to produce a resulting block from a data block, and that includes at least one stage and at least one other stage. The at least one stage is to select one of first operands and second operands input to the at least one other stage. The first and second operands are respectively associated with the first and second sets of operations, respectively. The at least one other stage involves arithmetic and logical operations common to both the first and second sets of operations. At least one other processing unit is to perform at least one set of cryptographic-related operations (different, at least in part, from the first and second sets of operations) on at least one of (1) another block to produce the data block and (2) the resulting block.
摘要翻译：一个实施例包括至少一个处理单元，用于执行至少第一和第二组扩散相关操作以从数据块产生结果块，并且其包括至少一个阶段和至少一个其他阶段。所述至少一个级是选择输入至少一个其他级的第一操作数和第二操作数之一。第一和第二操作数分别分别与第一和第二组操作相关联。所述至少一个其他阶段涉及对于第一和第二组操作共同的算术和逻辑运算。至少一个其他处理单元将在（1）另一个块中的至少一个上执行至少一组密码相关操作（至少部分地不同于第一和第二组操作），以产生数据块和（2）得到的块。

7. 发明申请

US20080147768A1 Configurable Exponent Fifo 有权
标题翻译：可配置指数
公开(公告)号：US20080147768A1
公开(公告)日：2008-06-19
申请号：US11610841
申请日：2006-12-14
申请人： Vinodh Gopal , Wajdi Feghali , Gilbert Wolrich , Daniel Cutter , Robert P. Ottavi
发明人： Vinodh Gopal , Wajdi Feghali , Gilbert Wolrich , Daniel Cutter , Robert P. Ottavi
IPC分类号： G06F7/38
CPC分类号： G06F7/723
摘要： The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second word into the first register and loading at least one bit from the second register into an arithmetic logic unit. The method may further include performing modular exponentiation on the at least one bit to generate a result and generating a public key based upon, at least in part, the result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行模幂运算的系统和方法。该方法包括将来自存储器的向量的第一字加载到第一寄存器中，并随后将第一个字从第一寄存器加载到第二寄存器。该方法还可以包括将第二字加载到第一寄存器中并将至少一个比特从第二寄存器加载到算术逻辑单元中。该方法还可以包括在至少一个比特上执行模幂运算以产生结果，并且至少部分地基于结果生成公开密钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

8. 发明授权

US08363828B2 Diffusion and cryptographic-related operations 有权
标题翻译：扩散和加密相关操作
公开(公告)号：US08363828B2
公开(公告)日：2013-01-29
申请号：US12368196
申请日：2009-02-09
申请人： Vinodh Gopal , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Robert Ottavi , Sean Gulley
发明人： Vinodh Gopal , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Robert Ottavi , Sean Gulley
IPC分类号： G06F21/00
CPC分类号： G09C1/00 , H04L9/0637 , H04L2209/12
摘要： An embodiment includes at least one processing unit to perform at least first and second sets of diffusion-related operations to produce a resulting block from a data block, and that includes at least one stage and at least one other stage. The at least one stage is to select one of first operands and second operands input to the at least one other stage. The first and second operands are respectively associated with the first and second sets of operations, respectively. The at least one other stage involves arithmetic and logical operations common to both the first and second sets of operations. At least one other processing unit is to perform at least one set of cryptographic-related operations (different, at least in part, from the first and second sets of operations) on at least one of (1) another block to produce the data block and (2) the resulting block.
摘要翻译：一个实施例包括至少一个处理单元，用于执行至少第一和第二组扩散相关操作以从数据块产生结果块，并且其包括至少一个阶段和至少一个其他阶段。所述至少一个级是选择输入至少一个其他级的第一操作数和第二操作数之一。第一和第二操作数分别分别与第一和第二组操作相关联。所述至少一个其他阶段涉及对于第一和第二组操作共同的算术和逻辑运算。至少一个其他处理单元将在（1）另一个块中的至少一个上执行至少一组密码相关操作（至少部分地不同于第一和第二组操作），以产生数据块和（2）得到的块。

9. 发明申请

US20110106872A1 Method and apparatus for providing an area-efficient large unsigned integer multiplier 审中-公开
标题翻译：用于提供面积效率大的无符号整数乘法器的方法和装置
公开(公告)号：US20110106872A1
公开(公告)日：2011-05-05
申请号：US12157074
申请日：2008-06-06
申请人： William Hasenplaugh , Gilbert Wolrich , Vinodh Gopal , Gunnar Gaubatz , Erdinc Ozturk , Wajdi Feghali
发明人： William Hasenplaugh , Gilbert Wolrich , Vinodh Gopal , Gunnar Gaubatz , Erdinc Ozturk , Wajdi Feghali
IPC分类号： G06F7/487
CPC分类号： G06F7/5324 , G06F7/72
摘要： An area efficient multiplier having high performance at modest clock speeds is presented. The performance of the multiplier is based on optimal choice of a number of levels of Karatsuba decomposition. The multiplier may be used to perform efficient modular reduction of large numbers greater than the size of the multiplier.
摘要翻译：提出了一种在适度的时钟速度下具有高性能的区域有效乘法器。乘数的表现是基于对Karatsuba分解的多个水平的最佳选择。乘法器可用于执行大于乘数大小的大数量的有效的模块化减少。

10. 发明申请

US20090158132A1 Determining a message residue 有权
标题翻译：确定消息残差
公开(公告)号：US20090158132A1
公开(公告)日：2009-06-18
申请号：US12291621
申请日：2008-11-12
申请人： Vinodh Gopal , Gilbert Wolrich , Wajdi Feghali , Erdinc Ozturk , Shay Gueron
发明人： Vinodh Gopal , Gilbert Wolrich , Wajdi Feghali , Erdinc Ozturk , Shay Gueron
IPC分类号： H03M13/09 , G06F7/72 , G06F17/14 , G06F11/10 , G06F5/01
CPC分类号： G06F7/724 , H03M13/091
摘要： In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format, and perform a polynomial multiplication of the first number and the at least a portion of the first number.
摘要翻译：在一个方面，用于确定相对于包括一系列段的消息的多项式的模块余数的电路。在另一方面，访问具有第一末端格式的第一号码的至少一部分的电路基于具有与第一末端格式相反的端格式的第三号码的位反射和位移来确定第二号码，以及执行第一数字和第一数字的至少一部分的多项式相乘。

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