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1. 发明授权

US08212413B2 Circuit assembly for gating a power semiconductor switch 有权
标题翻译：用于选通功率半导体开关的电路组件
公开(公告)号：US08212413B2
公开(公告)日：2012-07-03
申请号：US12557026
申请日：2009-09-10
申请人： Uwe Jansen , Ulrich Schwarzer , Reinhold Bayerer
发明人： Uwe Jansen , Ulrich Schwarzer , Reinhold Bayerer
IPC分类号： H04B15/00
CPC分类号： H02M1/08 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48472 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H02M2001/0006 , H03K17/567 , H03K2217/0081 , H01L2924/00014 , H01L2924/00
摘要： An embodiment of the invention relates to a circuit assembly having the following components: a power transistor with a control terminal, a first load terminal and a second load terminal, the second load terminal having a floating potential; a driver circuit configured to generate control signals for the control terminal of the power transistor, the relevant reference potential for the driver circuit being the floating potential of the second load terminal; a planar metallization layer sited on or in a substrate and comprising a constant reference potential, a shielding plane isolated from the metallization layer, sited planar on or in the substrate such that it is capacitively coupled to the metallization layer; a power supply circuit for providing a supply voltage referenced to the floating potential of the second load terminal for the driver circuit, the power supply circuit comprising, circuited between the second load terminal and the shielding plane, a first series circuit including a first capacitor and a first diode.
摘要翻译：本发明的实施例涉及具有以下部件的电路组件：具有控制端子的功率晶体管，第一负载端子和第二负载端子，所述第二负载端子具有浮置电位; 驱动电路，其被配置为产生用于所述功率晶体管的控制端子的控制信号，所述驱动电路的相关参考电位是所述第二负载端子的浮置电位; 平面金属化层位于衬底上或衬底中，并且包括恒定的参考电位，与金属化层隔离的屏蔽平面位于衬底上或衬底中，使得其电容耦合到金属化层; 电源电路，用于提供参考用于驱动电路的第二负载端子的浮动电位的电源电压，所述电源电路包括在第二负载端子和屏蔽平面之间的第二串联电路，第一串联电路包括第一电容器和第一个二极管。

2. 发明申请

US20100066175A1 CIRCUIT ASSEMBLY FOR GATING A POWER SEMICONDUCTOR SWITCH 有权
标题翻译：用于加电功率半导体开关的电路组件
公开(公告)号：US20100066175A1
公开(公告)日：2010-03-18
申请号：US12557026
申请日：2009-09-10
申请人： Uwe Jansen , Ulrich Schwarzer , Reinhold Bayerer
发明人： Uwe Jansen , Ulrich Schwarzer , Reinhold Bayerer
IPC分类号： H04B3/00
CPC分类号： H02M1/08 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48472 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H02M2001/0006 , H03K17/567 , H03K2217/0081 , H01L2924/00014 , H01L2924/00
摘要： An embodiment of the invention relates to a circuit assembly having the following components: a power transistor with a control terminal, a first load terminal and a second load terminal, the second load terminal having a floating potential; a driver circuit configured to generate control signals for the control terminal of the power transistor, the relevant reference potential for the driver circuit being the floating potential of the second load terminal; a planar metallization layer sited on or in a substrate and comprising a constant reference potential, a shielding plane isolated from the metallization layer, sited planar on or in the substrate such that it is capacitively coupled to the metallization layer; a power supply circuit for providing a supply voltage referenced to the floating potential of the second load terminal for the driver circuit, the power supply circuit comprising, circuited between the second load terminal and the shielding plane, a first series circuit including a first capacitor and a first diode.
摘要翻译：本发明的实施例涉及具有以下部件的电路组件：具有控制端子的功率晶体管，第一负载端子和第二负载端子，所述第二负载端子具有浮置电位; 驱动电路，其被配置为产生用于所述功率晶体管的控制端子的控制信号，所述驱动电路的相关参考电位是所述第二负载端子的浮置电位; 平面金属化层位于衬底上或衬底中，并且包括恒定的参考电位，与金属化层隔离的屏蔽平面位于衬底上或衬底中，使得其电容耦合到金属化层; 电源电路，用于提供参考用于驱动电路的第二负载端子的浮动电位的电源电压，所述电源电路包括在第二负载端子和屏蔽平面之间的第二串联电路，第一串联电路包括第一电容器和第一个二极管。

3. 发明申请

US20100085105A1 CIRCUIT ARRANGEMENT INCLUDING A VOLTAGE SUPPLY CIRCUIT AND SEMICONDUCTOR SWITCHING ELEMENT 有权
标题翻译：电路布置包括电源电路和半导体开关元件
公开(公告)号：US20100085105A1
公开(公告)日：2010-04-08
申请号：US12571114
申请日：2009-09-30
申请人： Reinhold Bayerer , Peter Kanschat , Uwe Jansen
发明人： Reinhold Bayerer , Peter Kanschat , Uwe Jansen
IPC分类号： H03K17/56
CPC分类号： H03K17/0406
摘要： A circuit arrangement comprising a first semiconductor switching element, which has a load path and a drive terminal. A voltage supply circuit, is provided including an inductance connected in series with the load path of the first semiconductor switching element, and a capacitive charge storage arrangement, which is connected in parallel with the inductance and which has a first and a second output terminal for providing a supply voltage.
摘要翻译：一种电路装置，包括具有负载路径和驱动端子的第一半导体开关元件。提供一种电压供给电路，包括与第一半导体开关元件的负载路径串联连接的电感和与电感并联连接的电容性电荷存储装置，具有第一和第二输出端子，提供电源电压。

4. 发明申请

US20120119721A1 CIRCUIT ARRANGEMENT INCLUDING VOLTAGE SUPPLY CIRCUIT 有权
标题翻译：包括电压供电电路的电路布置
公开(公告)号：US20120119721A1
公开(公告)日：2012-05-17
申请号：US13359150
申请日：2012-01-26
申请人： Reinhold Bayerer , Peter Kanschat , Uwe Jansen
发明人： Reinhold Bayerer , Peter Kanschat , Uwe Jansen
IPC分类号： G05F1/10
CPC分类号： H03K17/0406
摘要： A circuit arrangement comprising a first semiconductor switching element, which has a load path and a drive terminal. A voltage supply circuit, is provided including an inductance connected in series with the load path of the first semiconductor switching element, and a capacitive charge storage arrangement, which is connected in parallel with the inductance and which has a first and a second output terminal for providing a supply voltage.
摘要翻译：一种电路装置，包括具有负载路径和驱动端子的第一半导体开关元件。提供一种电压供给电路，包括与第一半导体开关元件的负载路径串联连接的电感和与电感并联连接的电容性电荷存储装置，具有第一和第二输出端子，提供电源电压。

5. 发明授权

US08344764B2 Circuit arrangement including voltage supply circuit 有权
标题翻译：电路布置包括电源电路
公开(公告)号：US08344764B2
公开(公告)日：2013-01-01
申请号：US13359150
申请日：2012-01-26
申请人： Reinhold Bayerer , Peter Kanschat , Uwe Jansen
发明人： Reinhold Bayerer , Peter Kanschat , Uwe Jansen
IPC分类号： H03K3/00
CPC分类号： H03K17/0406
摘要： A circuit arrangement comprising a first semiconductor switching element, which has a load path and a drive terminal. A voltage supply circuit, is provided including an inductance connected in series with the load path of the first semiconductor switching element, and a capacitive charge storage arrangement, which is connected in parallel with the inductance and which has a first and a second output terminal for providing a supply voltage.
摘要翻译：一种电路装置，包括具有负载路径和驱动端子的第一半导体开关元件。提供一种电压供给电路，包括与第一半导体开关元件的负载路径串联连接的电感和与电感并联连接的电容性电荷存储装置，具有第一和第二输出端子，提供电源电压。

6. 发明授权

US08120391B2 Circuit arrangement including a voltage supply circuit and semiconductor switching element 有权
标题翻译：电路装置包括电压供应电路和半导体开关元件
公开(公告)号：US08120391B2
公开(公告)日：2012-02-21
申请号：US12571114
申请日：2009-09-30
申请人： Reinhold Bayerer , Peter Kanschat , Uwe Jansen
发明人： Reinhold Bayerer , Peter Kanschat , Uwe Jansen
IPC分类号： H03K3/00
CPC分类号： H03K17/0406
摘要： A circuit arrangement comprising a first semiconductor switching element, which has a load path and a drive terminal. A voltage supply circuit, is provided including an inductance connected in series with the load path of the first semiconductor switching element, and a capacitive charge storage arrangement, which is connected in parallel with the inductance and which has a first and a second output terminal for providing a supply voltage.
摘要翻译：一种电路装置，包括具有负载路径和驱动端子的第一半导体开关元件。提供一种电压供给电路，包括与第一半导体开关元件的负载路径串联连接的电感和与电感并联连接的电容性电荷存储装置，具有第一和第二输出端子，提供电源电压。

7. 发明申请

US20070070567A1 DESATURATION CIRCUIT FOR AN IGBT 有权
标题翻译： IGBT绝缘电路
公开(公告)号：US20070070567A1
公开(公告)日：2007-03-29
申请号：US11534045
申请日：2006-09-21
申请人： Reinhold Bayerer , Uwe Jansen , Marco Bohllaender
发明人： Reinhold Bayerer , Uwe Jansen , Marco Bohllaender
IPC分类号： H02H3/00
CPC分类号： H03K17/0828 , H03K17/0422 , H03K17/107
摘要： A desaturation circuit for an IGBT is disclosed. In one embodiment, flooding of the component with charge carriers is reduced before the IGBT is turned off.
摘要翻译：公开了一种用于IGBT的去饱和电路。在一个实施例中，在IGBT关断之前，减少了具有电荷载流子的部件的溢流。

8. 发明授权

US07724065B2 Desaturation circuit for an IGBT 有权
标题翻译： IGBT的去饱和电路
公开(公告)号：US07724065B2
公开(公告)日：2010-05-25
申请号：US11534045
申请日：2006-09-21
申请人： Reinhold Bayerer , Uwe Jansen , Marco Bohllaender
发明人： Reinhold Bayerer , Uwe Jansen , Marco Bohllaender
IPC分类号： H03K17/04
CPC分类号： H03K17/0828 , H03K17/0422 , H03K17/107
摘要： A desaturation circuit for an IGBT is disclosed. In one embodiment, flooding of the component with charge carriers is reduced before the IGBT is turned off.
摘要翻译：公开了一种用于IGBT的去饱和电路。在一个实施例中，在IGBT关断之前，减少了具有电荷载流子的部件的溢流。

9. 发明授权

US09688060B2 Method for producing a composite and a power semiconductor module 有权
公开(公告)号：US09688060B2
公开(公告)日：2017-06-27
申请号：US13571417
申请日：2012-08-10
申请人： Reinhold Bayerer , Olaf Hohlfeld
发明人： Reinhold Bayerer , Olaf Hohlfeld
IPC分类号： B23K37/04 , H01L21/58 , B29C65/02 , H01L21/30 , B32B37/10 , H01L21/50 , H01L25/07 , H01L25/00 , H01L21/56 , H01L23/373 , H01L23/00
CPC分类号： B32B37/10 , H01L21/50 , H01L21/566 , H01L23/3735 , H01L24/75 , H01L24/83 , H01L25/072 , H01L25/50 , H01L2224/29339 , H01L2224/32225 , H01L2224/75102 , H01L2224/7511 , H01L2224/75265 , H01L2224/75317 , H01L2224/81191 , H01L2224/81192 , H01L2224/83007 , H01L2224/83801 , H01L2224/83825 , H01L2224/8384 , H01L2224/8385 , H01L2924/01327 , H01L2924/15787 , H01L2924/00 , H01L2924/00014
摘要： A composite is produced by providing a first and a second joining partner, a connecting means, a sealing means, a reactor having a pressure chamber, and a heating element. The two joining partners and the connecting means are arranged in the pressure chamber such that the connecting means is situated between the first joining partner and the second joining partner. A gas-tight region is then produced, in which the connecting means is arranged. Afterward, a gas pressure of at least 20 bar is produced in the pressure chamber outside the gas-tight region. The gas pressure acts on the gas-tight region and presses the first joining partner, the second joining partner and the connecting means together. The joining partners and the connecting means are then heated by means of the heating element to a predefined maximum temperature of at least 210° C. and then cooled.

10. 发明授权

US09196562B2 Semiconductor arrangement, semiconductor module, and method for connecting a semiconductor chip to a ceramic substrate 有权
标题翻译：半导体装置，半导体模块以及将半导体芯片连接到陶瓷基板的方法
公开(公告)号：US09196562B2
公开(公告)日：2015-11-24
申请号：US13226981
申请日：2011-09-07
申请人： Dirk Siepe , Reinhold Bayerer
发明人： Dirk Siepe , Reinhold Bayerer
IPC分类号： H01L23/15 , H01L23/373 , H01L23/00 , H01L25/07
CPC分类号： H01L23/3735 , H01L24/03 , H01L24/05 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L24/83 , H01L24/85 , H01L25/072 , H01L2224/04042 , H01L2224/05082 , H01L2224/05171 , H01L2224/05172 , H01L2224/05181 , H01L2224/05184 , H01L2224/05647 , H01L2224/05666 , H01L2224/32225 , H01L2224/32245 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48472 , H01L2224/48491 , H01L2224/48747 , H01L2224/48766 , H01L2224/48847 , H01L2224/48866 , H01L2224/49 , H01L2224/73265 , H01L2224/78313 , H01L2224/82105 , H01L2224/82106 , H01L2224/83801 , H01L2224/8383 , H01L2224/8384 , H01L2224/8501 , H01L2224/85205 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/0105 , H01L2924/0106 , H01L2924/01068 , H01L2924/0107 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/10253 , H01L2924/13055 , H01L2924/15787 , H01L2924/2076 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2924/00015 , H01L2224/83205
摘要： A semiconductor arrangement includes a silicon body having a top surface and a bottom surface, and a thick metal layer arranged on the top surface of the silicon body. The thick metal layer has a bonding surface facing away from the top surface of the silicon body. A bonding wire or a ribbon is bonded to the thick metal layer at the bonding surface of the thick metal layer. The thickness of the thick metal layer is at least 10 micrometers (μm), the thick metal layer comprises copper or a copper alloy, and the bonding wire or ribbon comprises copper or a copper-based material.
摘要翻译：半导体装置包括具有顶表面和底表面的硅体，以及布置在硅体顶表面上的厚金属层。厚金属层具有背离硅体的顶表面的接合表面。接合线或带在厚金属层的接合面接合到厚金属层。厚金属层的厚度为至少10微米（μm），厚金属层包括铜或铜合金，并且接合线或带包括铜或铜基材料。

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