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1. 发明授权

US08895384B2 Gate structures and methods of manufacture 有权
标题翻译：门结构和制造方法
公开(公告)号：US08895384B2
公开(公告)日：2014-11-25
申请号：US13293210
申请日：2011-11-10
申请人： Unoh Kwon , Ramachandran Muralidhar , Viorel Ontalus
发明人： Unoh Kwon , Ramachandran Muralidhar , Viorel Ontalus
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L27/0922 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L29/42364
摘要： A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material.
摘要翻译：提供了具有通道材料的金属栅极结构及其制造方法。该方法包括在衬底上形成虚拟栅极结构。该方法还包括在虚拟栅极结构的侧壁上形成侧壁结构。该方法还包括去除伪栅极结构以形成由侧壁结构限定的第一沟槽和第二沟槽。该方法还包括在第一沟槽和第二沟槽中的衬底上形成沟道材料。该方法还包括在第一沟槽被掩蔽的同时从第二沟槽去除沟道材料。该方法还包括用栅极材料填充第一沟槽和第二沟槽的剩余部分。

2. 发明申请

US20130119473A1 GATE STRUCTURES AND METHODS OF MANUFACTURE 有权
公开(公告)号：US20130119473A1
公开(公告)日：2013-05-16
申请号：US13293210
申请日：2011-11-10
申请人： Unoh Kwon , Ramachandran Muralidhar , Viorel Ontalus
发明人： Unoh Kwon , Ramachandran Muralidhar , Viorel Ontalus
IPC分类号： H01L21/8234 , H01L27/088 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L29/42364
摘要： A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material.

3. 发明申请

US20110269276A1 METHOD TO OPTIMIZE WORK FUNCTION IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) STRUCTURES 有权
标题翻译：补充金属氧化物半导体（CMOS）结构中的工作功能的优化方法
公开(公告)号：US20110269276A1
公开(公告)日：2011-11-03
申请号：US12770792
申请日：2010-04-30
申请人： Unoh Kwon , Dechao Guo , Siddarth A. Krishnan , Ramachandran Muralidhar
发明人： Unoh Kwon , Dechao Guo , Siddarth A. Krishnan , Ramachandran Muralidhar
IPC分类号： H01L21/8238 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L29/1054 , H01L29/42372 , H01L29/665 , H01L29/6656 , H01L29/7843
摘要： In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer.
摘要翻译：在一个实施例中，形成互补金属氧化物半导体（CMOS）器件的方法包括提供包括第一器件区域和第二器件区域的半导体衬底。使用栅极结构第一工艺在第一器件区域或第二器件区域之一中形成n型导电性半导体器件，其中n型导电性半导体器件包括具有n型功函数金属层的栅极结构。使用栅极结构最后工艺在第一器件区域或第二器件区域中的另一个中形成p型导电性半导体器件，其中p型导电半导体器件包括具有p型功函数金属层。

4. 发明授权

US08354313B2 Method to optimize work function in complementary metal oxide semiconductor (CMOS) structures 有权
标题翻译：在互补金属氧化物半导体（CMOS）结构中优化功函数的方法
公开(公告)号：US08354313B2
公开(公告)日：2013-01-15
申请号：US12770792
申请日：2010-04-30
申请人： Unoh Kwon , Dechao Guo , Siddarth A. Krishnan , Ramachandran Muralidhar
发明人： Unoh Kwon , Dechao Guo , Siddarth A. Krishnan , Ramachandran Muralidhar
IPC分类号： H01L21/8236 , H01L21/8234 , H01L21/4763
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L29/1054 , H01L29/42372 , H01L29/665 , H01L29/6656 , H01L29/7843
摘要： In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer.
摘要翻译：在一个实施例中，形成互补金属氧化物半导体（CMOS）器件的方法包括提供包括第一器件区域和第二器件区域的半导体衬底。使用栅极结构第一工艺在第一器件区域或第二器件区域之一中形成n型导电性半导体器件，其中n型导电性半导体器件包括具有n型功函数金属层的栅极结构。使用栅极结构最后工艺在第一器件区域或第二器件区域中的另一个中形成p型导电性半导体器件，其中p型导电半导体器件包括具有p型功函数金属层。

5. 发明授权

US08941177B2 Semiconductor devices having different gate oxide thicknesses 有权
公开(公告)号：US08941177B2
公开(公告)日：2015-01-27
申请号：US13534012
申请日：2012-06-27
申请人： Charlotte DeWan Adams , Michael P. Chudzik , Siddarth A. Krishnan , Unoh Kwon , Shahab Siddiqui
发明人： Charlotte DeWan Adams , Michael P. Chudzik , Siddarth A. Krishnan , Unoh Kwon , Shahab Siddiqui
IPC分类号： H01L29/36 , H01L29/66
CPC分类号： H01L27/0886 , H01L21/845 , H01L27/1211 , H01L29/42364 , H01L29/66545 , H01L29/66795
摘要： A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.

6. 发明授权

US08716813B2 Scaled equivalent oxide thickness for field effect transistor devices 失效
标题翻译：场效应晶体管器件的等效氧化物厚度变化
公开(公告)号：US08716813B2
公开(公告)日：2014-05-06
申请号：US13556333
申请日：2012-07-24
申请人： Takashi Ando , Changhwan Choi , Unoh Kwon , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Unoh Kwon , Vijay Narayanan
IPC分类号： H01L29/78
CPC分类号： H01L21/823842 , H01L21/02164 , H01L21/02697 , H01L21/28229 , H01L21/823857 , H01L29/517 , H01L29/518
摘要： A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first TiN layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second TiN layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion.
摘要翻译：场效应晶体管器件包括：第一栅堆叠部分，包括设置在衬底上的电介质层，设置在电介质层上的第一TiN层，设置在电介质层上的金属层和设置在金属层上的第二TiN层，与第一栅叠层部相邻设置的第一源极区域和与第一栅极堆叠部分相邻设置的第一漏极区域。

7. 发明授权

US08629014B2 Replacement metal gate structures for effective work function control 有权
标题翻译：更换金属门结构，实现有效的工作功能控制
公开(公告)号：US08629014B2
公开(公告)日：2014-01-14
申请号：US12885592
申请日：2010-09-20
申请人： Unoh Kwon , Michael P. Chudzik , Ravikumar Ramachandran
发明人： Unoh Kwon , Michael P. Chudzik , Ravikumar Ramachandran
IPC分类号： H01L21/8238 , H01L21/70
CPC分类号： H01L27/0922 , H01L21/823842
摘要： A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures.
摘要翻译：在替换金属栅极方案中沉积阻挡金属层和第一型功函数金属层的堆叠。阻挡金属层可以直接沉积在栅极介电层上。图案化第一型功函数金属层仅存在于第一类场效应晶体管的区域中。第二类功函数金属层直接沉积在第二类场效应晶体管的区域中的势垒金属层上。或者，第一类功函数层可以直接沉积在栅介电层上。图案化阻挡金属层仅存在于第一类场效应晶体管的区域中。第二类型功函数金属层直接沉积在第二类场效应晶体管的区域中的栅介质层上。导电材料填充和平坦化形成双重功能替代栅极结构。

8. 发明授权

US08546211B2 Replacement gate having work function at valence band edge 有权
公开(公告)号：US08546211B2
公开(公告)日：2013-10-01
申请号：US12948031
申请日：2010-11-17
申请人： Keith Kwong Hon Wong , Michael P. Chudzik , Unoh Kwon
发明人： Keith Kwong Hon Wong , Michael P. Chudzik , Unoh Kwon
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L29/165 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.

9. 发明授权

US08450169B2 Replacement metal gate structures providing independent control on work function and gate leakage current 失效
标题翻译：替代金属栅极结构提供对功函数和栅极漏电流的独立控制
公开(公告)号：US08450169B2
公开(公告)日：2013-05-28
申请号：US12954946
申请日：2010-11-29
申请人： Unoh Kwon , Ramachandra Divakaruni , Siddarth A. Krishnan , Ravikumar Ramachandran
发明人： Unoh Kwon , Ramachandra Divakaruni , Siddarth A. Krishnan , Ravikumar Ramachandran
IPC分类号： H01L21/8238
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L27/088 , H01L27/0922 , H01L29/49 , H01L29/513 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.
摘要翻译：可以通过平面高介电常数材料部分为不同类型的场效应晶体管选择栅极电介质的厚度和组成，其可以仅针对选定类型的场效应晶体管提供。此外，场效应晶体管的工作功能可以独立于栅极电介质的材料堆叠的选择而被调整。在去除一次性栅极材料部分之后，在凹入的栅极腔内的栅极电介质层上沉积阻挡金属层和第一类型功函数金属层的堆叠。图案化第一型功函数金属层之后，第二类功函数金属层直接沉积在第二类场效应晶体管的区域中的阻挡金属层上。导电材料填充栅极腔，随后的平坦化工艺形成双功能金属栅极结构。

10. 发明授权

US08232148B2 Structure and method to make replacement metal gate and contact metal 有权
标题翻译：用于替换金属栅极和接触金属的结构和方法
公开(公告)号：US08232148B2
公开(公告)日：2012-07-31
申请号：US12717398
申请日：2010-03-04
申请人： Zhengwen Li , Michael P. Chudzik , Unoh Kwon , Filippos Papadatos , Andrew H. Simon , Keith Kwong Hon Wong
发明人： Zhengwen Li , Michael P. Chudzik , Unoh Kwon , Filippos Papadatos , Andrew H. Simon , Keith Kwong Hon Wong
IPC分类号： H01L21/00
CPC分类号： H01L23/485 , H01L21/28088 , H01L21/28202 , H01L21/76283 , H01L21/76877 , H01L21/823842 , H01L21/823871 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： An electrical device is provided with a p-type semiconductor device having a first gate structure that includes a gate dielectric on top of a semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.
摘要翻译：电气装置设置有具有第一栅极结构的p型半导体器件，其包括在半导体衬底的顶部上的栅极电介质，p型功函数金属层，由钛和铝构成的金属层，以及金属填充铝。 n型半导体器件也存在于半导体衬底上，该半导体衬底包括第二栅极结构，其包括栅极电介质，由钛和铝构成的金属层以及由铝组成的金属填充物。层间电介质存在于半导体衬底上。层间电介质包括到p型和n型半导体器件的源区和漏区的互连。互连由钛和铝构成的金属层和由铝组成的金属填充物构成。本公开还提供了形成上述结构的方法。

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