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1. 发明授权

US07630270B2 Dual mode SRAM architecture for voltage scaling and power management 有权
标题翻译：用于电压缩放和电源管理的双模式SRAM架构
公开(公告)号：US07630270B2
公开(公告)日：2009-12-08
申请号：US11841310
申请日：2007-08-20
申请人： Uming Ko , Gordon Gammie , Sumanth K. Gururajarao
发明人： Uming Ko , Gordon Gammie , Sumanth K. Gururajarao
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C7/02 , G11C11/413
摘要： The present disclosure provides a dual-mode voltage controller, a method of supplying voltage to SRAM periphery circuits and an integrated circuit. In one embodiment, the dual-mode voltage controller is for use with an SRAM array and includes a voltage switching unit connected to a digital core voltage and an SRAM array voltage to form a structure capable of switching at least one SRAM periphery circuit between the digital core voltage and the SRAM array voltage.
摘要翻译：本公开提供了一种双模电压控制器，向SRAM外围电路提供电压的方法和集成电路。在一个实施例中，双模式电压控制器用于与SRAM阵列一起使用，并且包括连接到数字核心电压和SRAM阵列电压的电压切换单元，以形成能够在数字电源之间切换至少一个SRAM外围电路的结构核心电压和SRAM阵列电压。

2. 发明申请

US20080043560A1 DUAL MODE SRAM ARCHITECTURE FOR VOLTAGE SCALING AND POWER MANAGEMENT 有权
标题翻译：用于电压调节和电源管理的双模SRAM架构
公开(公告)号：US20080043560A1
公开(公告)日：2008-02-21
申请号：US11841310
申请日：2007-08-20
申请人： Uming Ko , Gordon Gammie , Sumanth K. Gururajarao
发明人： Uming Ko , Gordon Gammie , Sumanth K. Gururajarao
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C7/02 , G11C11/413
摘要： The present disclosure provides a dual-mode voltage controller, a method of supplying voltage to SRAM periphery circuits and an integrated circuit. In one embodiment, the dual-mode voltage controller is for use with an SRAM array and includes a voltage switching unit connected to a digital core voltage and an SRAM array voltage to form a structure capable of switching at least one SRAM periphery circuit between the digital core voltage and the SRAM array voltage.
摘要翻译：本公开提供了一种双模电压控制器，向SRAM外围电路提供电压的方法和集成电路。在一个实施例中，双模式电压控制器用于与SRAM阵列一起使用，并且包括连接到数字核心电压和SRAM阵列电压的电压切换单元，以形成能够在数字电路之间切换至少一个SRAM外围电路的结构核心电压和SRAM阵列电压。

3. 发明申请

US20100103760A1 Memory Power Management Systems and Methods 有权
标题翻译：内存电源管理系统和方法
公开(公告)号：US20100103760A1
公开(公告)日：2010-04-29
申请号：US12258747
申请日：2008-10-27
申请人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
发明人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
IPC分类号： G11C5/14 , G11C8/00
CPC分类号： G11C5/147
摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
摘要翻译：提供了内存电源管理系统和方法。本发明的一个实施例包括存储器电源管理系统。该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

4. 发明申请

US20110216619A1 MEMORY POWER MANAGEMENT SYSTEMS AND METHODS 审中-公开
标题翻译：存储电源管理系统和方法
公开(公告)号：US20110216619A1
公开(公告)日：2011-09-08
申请号：US13106612
申请日：2011-05-12
申请人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
发明人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
摘要翻译：提供了内存电源管理系统和方法。本发明的一个实施例包括存储器电源管理系统。该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

5. 发明申请

US20090039952A1 System and Method for Auto-Power Gating Synthesis for Active Leakage Reduction 有权
标题翻译：用于主动泄漏减少的自动门控合成系统和方法
公开(公告)号：US20090039952A1
公开(公告)日：2009-02-12
申请号：US11947012
申请日：2007-11-29
申请人： Alice Wang , Hugh T. Mair , Gordon Gammie , Uming Ko
发明人： Alice Wang , Hugh T. Mair , Gordon Gammie , Uming Ko
IPC分类号： G05F1/10 , G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.
摘要翻译：一种方法包括解析集成电路的设计以定义自动功率选通电源域中的单元，从集成电路的解析设计中自动创建自动电源门控功率域网表，以及将自动电源门控功率域网表放置和布线生成集成电路的布局。解析将集成电路的高级电源域分成一个或多个自动电源门控电源域。自动功率门控功率域具有基本上零周期的上电时间，从而实现透明操作。此外，自动电源门控功率域可以自动插入到集成电路的设计中，从而减轻集成电路设计人员插入电源域和相关硬件和软件的任务。

6. 发明授权

US07920020B2 System and method for auto-power gating synthesis for active leakage reduction 有权
标题翻译：用于自动电源门控合成的系统和方法，用于主动泄漏减少
公开(公告)号：US07920020B2
公开(公告)日：2011-04-05
申请号：US12814195
申请日：2010-06-11
申请人： Alice Wang , Hugh T. Mair , Gordon Gammie , Uming Ko
发明人： Alice Wang , Hugh T. Mair , Gordon Gammie , Uming Ko
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.
摘要翻译：一种方法包括解析集成电路的设计以在自动功率选通电源域中定义单元，从集成电路的解析设计中自动创建自动电源门控功率域网表，以及将自动电源门控功率域网表放置和布线生成集成电路的布局。解析将集成电路的高级电源域分成一个或多个自动电源门控电源域。自动功率门控功率域具有基本上零周期的上电时间，从而实现透明操作。此外，自动电源门控功率域可以自动插入到集成电路的设计中，从而减轻集成电路设计人员插入电源域和相关硬件和软件的任务。

7. 发明授权

US07760011B2 System and method for auto-power gating synthesis for active leakage reduction 有权
标题翻译：用于自动电源门控合成的系统和方法，用于主动泄漏减少
公开(公告)号：US07760011B2
公开(公告)日：2010-07-20
申请号：US11947012
申请日：2007-11-29
申请人： Alice Wang , Hugh T. Mair , Gordon Gammie , Uming Ko
发明人： Alice Wang , Hugh T. Mair , Gordon Gammie , Uming Ko
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.
摘要翻译：一种方法包括解析集成电路的设计以在自动功率选通电源域中定义单元，从集成电路的解析设计中自动创建自动电源门控功率域网表，以及将自动电源门控功率域网表放置和布线生成集成电路的布局。解析将集成电路的高级电源域分成一个或多个自动电源门控电源域。自动功率门控功率域具有基本上零周期的上电时间，从而实现透明操作。此外，自动电源门控功率域可以自动插入到集成电路的设计中，从而减轻集成电路设计人员插入电源域和相关硬件和软件的任务。

8. 发明授权

US10275010B2 Fast and Autonomous mechanism for CPU OC protection 有权
公开(公告)号：US10275010B2
公开(公告)日：2019-04-30
申请号：US15119731
申请日：2015-02-16
申请人： MediaTek Singapore Pte. Ltd. , Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist
发明人： Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist
IPC分类号： G06F1/32 , G06F1/324 , G06F1/28 , G06F1/3206 , G06F1/3296
摘要： A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.

9. 发明申请

US20170068296A1 Fast and Autonomous Mechanism for CPU OC Protection 审中-公开
标题翻译：快速自主的CPU OC保护机制
公开(公告)号：US20170068296A1
公开(公告)日：2017-03-09
申请号：US15119731
申请日：2015-02-16
申请人： Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist , MediaTek Singapore Pte. Ltd.
发明人： Hugh Thomas Mair , Sumanth Katte Gururajarao , Gordon Gammie , Alice Wang , Uming Ko , Rolf Lagerquist
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/28 , G06F1/3206 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.
摘要翻译：提供了一种检测和防止过电流引起的系统故障的方法。 OC保护控制器根据接收到的CPU活动信息监视CPU总功耗。响应监视，如果CPU功耗超过阈值，则OC保护控制器输出频率抖动控制信号，以降低CPU时钟频率，使CPU不达到OC限制。 OC保护控制器还输出PLL频率控制信号，以减少PLL时钟频率，提高系统效率。

10. 发明授权

US07961546B2 Memory power management systems and methods 有权
标题翻译：内存电源管理系统和方法
公开(公告)号：US07961546B2
公开(公告)日：2011-06-14
申请号：US12258747
申请日：2008-10-27
申请人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
发明人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
摘要翻译：提供了内存电源管理系统和方法。本发明的一个实施例包括存储器电源管理系统。该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。该系统还包括第二LDO调节器，其提供从第二电源电压导出的最小存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

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