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1. 发明授权

US06924196B1 Anti-reflective coating and process using an anti-reflective coating 有权
标题翻译：抗反射涂层和使用防反射涂层的工艺
公开(公告)号：US06924196B1
公开(公告)日：2005-08-02
申请号：US09370508
申请日：1999-08-06
申请人： Umesh Sharma , Kevin Q. Yin , Hong J. Wu , Suryanarayana Shivakumar Bhattacharya , Xiaoming Li
发明人： Umesh Sharma , Kevin Q. Yin , Hong J. Wu , Suryanarayana Shivakumar Bhattacharya , Xiaoming Li
IPC分类号： H01L21/28 , H01L21/311 , H01L21/314 , H01L21/3213 , H01L21/336 , H01L21/8247
CPC分类号： H01L27/11526 , H01L21/28273 , H01L21/31111 , H01L21/3144 , H01L21/3145 , H01L21/32139 , H01L27/11534 , H01L29/66825
摘要： An anti-reflective coating for use in the fabrication of a semiconductor device includes a thin oxide layer and an overlying layer of silicon oxynitride. The anti-reflective layer is advantageously used in the fabrication of FLASH memory devices which include a layer of polycrystalline silicon and an underlying layer of silicon nitride. After being used to pattern the polycrystalline silicon and silicon nitride, the anti-reflective coating is removed in a solution of hot phosphoric acid with the removal taking place before the silicon oxynitride is exposed to any elevated temperatures.
摘要翻译：用于制造半导体器件的抗反射涂层包括薄氧化物层和氮氧化硅上覆层。抗反射层有利地用于制造包括多晶硅层和氮化硅的下层的闪存存储器件。在用于对多晶硅和氮化硅进行图案化之后，在热磷酸溶液中除去抗反射涂层，在氮氧化硅暴露于任何升高的温度之前进行去除。

2. 发明授权

US06995449B1 Deep trench isolation region with reduced-size cavities in overlying field oxide 有权
标题翻译：深沟槽隔离区域，覆盖场氧化物中具有较小尺寸的空腔
公开(公告)号：US06995449B1
公开(公告)日：2006-02-07
申请号：US10842943
申请日：2004-05-10
申请人： Kevin Q. Yin , Amol Kalburge
发明人： Kevin Q. Yin , Amol Kalburge
IPC分类号： H01L29/00
CPC分类号： H01L21/8249 , H01L21/76202 , H01L21/763
摘要： According to an exemplary method for removing a hard mask in a deep trench isolation process, a hard mask is formed over the substrate, where the substrate includes at least one field oxide region. Thereafter, a trench is formed in the substrate, where the trench has a first sidewall and a second sidewall. According to this exemplary embodiment, the hard mask is removed after forming the trench. The hard mask may be removed by, for example, etching the hard mask in an anisotropic dry etch process, where the anisotropic dry etch process is selective to nitride and silicon. Next, an oxide liner is deposited by a CVD process on the first and second sidewalls of the trench and over the substrate after the hard mask has been removed.
摘要翻译：根据用于在深沟槽隔离工艺中去除硬掩模的示例性方法，在衬底上形成硬掩模，其中衬底包括至少一个场氧化物区域。此后，在衬底中形成沟槽，其中沟槽具有第一侧壁和第二侧壁。根据该示例性实施例，在形成沟槽之后去除硬掩模。可以通过例如在各向异性干蚀刻工艺中蚀刻硬掩模来除去硬掩模，其中各向异性干蚀刻工艺对氮化物和硅是选择性的。接下来，在去除硬掩模之后，通过CVD工艺将氧化物衬垫沉积在沟槽的第一和第二侧壁上以及衬底上。

3. 发明授权

US06830967B1 Method for forming CMOS transistor spacers in a BiCMOS process 有权
标题翻译：在BiCMOS工艺中形成CMOS晶体管间隔物的方法
公开(公告)号：US06830967B1
公开(公告)日：2004-12-14
申请号：US10262714
申请日：2002-10-02
申请人： Kevin Q. Yin , Amol M. Kalburge , Klaus F. Schuegraf
发明人： Kevin Q. Yin , Amol M. Kalburge , Klaus F. Schuegraf
IPC分类号： H01L218238
CPC分类号： H01L21/8249
摘要： According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example, be TEOS silicon dioxide. Thereafter, a conformal layer is deposited over the substrate and the transistor gate. The conformal layer may, for example, be silicon nitride. An opening is then etched in the conformal layer. Next, a base layer is deposited on the conformal layer and in the opening. The base layer may, for example, be silicon-germanium. According to this exemplary embodiment, an emitter may be formed on the base layer in the opening. Next, the base layer is removed from the conformal layer. The conformal layer is then etched back to form a spacer adjacent to the transistor gate. In one embodiment, a structure is fabricated according to the above described exemplary method.
摘要翻译：根据一个实施例中的示例性方法，在衬底上制造晶体管栅极。接下来，可以在衬底上沉积蚀刻停止层。蚀刻停止层可以例如是TEOS二氧化硅。此后，在衬底和晶体管栅极上沉积保形层。保形层可以是例如氮化硅。然后在共形层中蚀刻开口。接下来，在保形层和开口中沉积基层。基底层可以例如是硅 - 锗。根据该示例性实施例，可以在开口中的基底层上形成发射器。接下来，从保形层去除基层。然后将保形层回蚀刻以形成与晶体管栅极相邻的间隔物。在一个实施例中，根据上述示例性方法制造结构。

4. 发明授权

US06764913B1 Method for controlling an emitter window opening in an HBT and related structure 有权
标题翻译：用于控制HBT和相关结构中的发射器窗口开口的方法
公开(公告)号：US06764913B1
公开(公告)日：2004-07-20
申请号：US10369027
申请日：2003-02-19
申请人： Amol M. Kalburge , Kevin Q. Yin , Klaus F. Schuegraf
发明人： Amol M. Kalburge , Kevin Q. Yin , Klaus F. Schuegraf
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L29/0804
摘要： According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the top surface of the base. The heterojunction bipolar transistor further comprises an intermediate oxide layer situated on the first and second oxide spacers. The heterojunction bipolar transistor further comprises an amorphous layer situated on the intermediate oxide layer. The heterojunction bipolar transistor further comprises an antireflective coating layer on the amorphous layer. The heterojunction bipolar transistor further comprises an emitter window opening situated between the first and second spacers, where the emitter window opening is defined by the top surface of the base, the first and second spacers, the intermediate oxide layer, the amorphous layer, and the antireflective coating layer. The heterojunction bipolar transistor may further comprise an emitter situated in the emitter window opening.
摘要翻译：根据一个示例性实施例，异质结双极晶体管包括具有顶表面的基极。异质结双极晶体管还包括第一间隔物和位于基底顶表面上的第二间隔物。异质结双极晶体管还包括位于第一和第二氧化物间隔物上的中间氧化物层。异质结双极晶体管还包括位于中间氧化物层上的非晶层。异质结双极晶体管还包括在非晶层上的抗反射涂层。异质结双极晶体管还包括位于第一和第二间隔物之间的发射器窗口，其中发射器窗口由基底的顶表面，第一和第二间隔物，中间氧化物层，非晶层和防反射涂层。异质结双极晶体管还可以包括位于发射器窗口中的发射器。

5. 发明授权

US07994611B1 Bipolar transistor fabricated in a biCMOS process 有权
标题翻译：双相晶体管采用biCMOS工艺制造
公开(公告)号：US07994611B1
公开(公告)日：2011-08-09
申请号：US10892015
申请日：2004-07-14
申请人： Kevin Q. Yin , Amol Kalburge , Kenneth M. Ring
发明人： Kevin Q. Yin , Amol Kalburge , Kenneth M. Ring
IPC分类号： H01L29/73
CPC分类号： H01L29/66287 , H01L21/8249 , H01L29/0804 , H01L29/66242
摘要： According to one exemplary embodiment, a bipolar transistor includes a base having a top surface. The bipolar transistor further includes a base oxide layer situated on the top surface of the base. The bipolar transistor further includes an antireflective coating layer situated on the base oxide layer. The bipolar transistor further includes an emitter situated over the top surface of the base and the antireflective coating layer, where a layer of polysilicon is not situated between the base oxide layer and the emitter.
摘要翻译：根据一个示例性实施例，双极晶体管包括具有顶表面的基座。双极晶体管还包括位于基底的顶表面上的基底氧化物层。双极晶体管还包括位于基底氧化物层上的抗反射涂层。双极晶体管还包括位于基极的顶表面和抗反射涂层之上的发射器，其中多晶硅层不位于基底氧化物层和发射极之间。

6. 发明授权

US06797580B1 Method for fabricating a bipolar transistor in a BiCMOS process and related structure 有权
标题翻译： BiCMOS工艺制造双极晶体管及相关结构的方法
公开(公告)号：US06797580B1
公开(公告)日：2004-09-28
申请号：US10371706
申请日：2003-02-21
申请人： Kevin Q. Yin , Amol Kalburge , Kenneth M. Ring
发明人： Kevin Q. Yin , Amol Kalburge , Kenneth M. Ring
IPC分类号： H01L21331
CPC分类号： H01L29/66287 , H01L21/8249 , H01L29/0804 , H01L29/66242
摘要： According to one exemplary embodiment, a method for fabricating a bipolar transistor in a BiCMOS process comprises a step of forming an emitter window stack by sequentially depositing a base oxide layer and an antireflective coating layer on a top surface of a base, where the emitter window stack does not comprise a polysilicon layer. The method further comprises etching an emitter window opening in the emitter window stack. The method further comprises depositing an emitter layer in the emitter window opening and over the antireflective coating layer and etching the emitter layer to form an emitter. The method further comprises etching a first portion of the base oxide layer not covered by the emitter using a first etchant, thereby causing the first portion of the base oxide layer to have a thickness less than a thickness of a second portion of the base oxide layer covered by the emitter.
摘要翻译：根据一个示例性实施例，在BiCMOS工艺中制造双极晶体管的方法包括通过在基底的顶表面上依次沉积基底氧化物层和抗反射涂层来形成发射器窗口叠层的步骤，其中发射极窗口堆叠不包括多晶硅层。该方法还包括蚀刻发射器窗口叠层中的发射器窗口。该方法还包括在发射器窗口和防反射涂层之上沉积发射极层并蚀刻发射极层以形成发射极。该方法还包括使用第一蚀刻剂蚀刻未被发射体覆盖的基底氧化物层的第一部分，从而使得基底氧化物层的第一部分具有小于基底氧化物层的第二部分的厚度的厚度被发射器覆盖。

7. 发明授权

US06586307B1 Method for controlling an emitter window opening in an HBT and related structure 失效
标题翻译：用于控制HBT和相关结构中的发射器窗口开口的方法
公开(公告)号：US06586307B1
公开(公告)日：2003-07-01
申请号：US10075701
申请日：2002-02-14
申请人： Amol M. Kalburge , Kevin Q. Yin , Klaus F. Schuegraf
发明人： Amol M. Kalburge , Kevin Q. Yin , Klaus F. Schuegraf
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L29/0804
摘要： According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the top surface of the base. The heterojunction bipolar transistor further comprises an intermediate oxide layer situated on the first and second oxide spacers. The heterojunction bipolar transistor further comprises an amorphous layer situated on the intermediate oxide layer. The heterojunction bipolar transistor further comprises an antireflective coating layer on the amorphous layer. The heterojunction bipolar transistor further comprises an emitter window opening situated between the first and second spacers, where the emitter window opening is defined by the top surface of the base, the first and second spacers, the intermediate oxide layer, the amorphous layer, and the antireflective coating layer. The heterojunction bipolar transistor may further comprise an emitter situated in the emitter window opening.
摘要翻译：根据一个示例性实施例，异质结双极晶体管包括具有顶表面的基极。异质结双极晶体管还包括第一间隔物和位于基底顶表面上的第二间隔物。异质结双极晶体管还包括位于第一和第二氧化物间隔物上的中间氧化物层。异质结双极晶体管还包括位于中间氧化物层上的非晶层。异质结双极晶体管还包括在非晶层上的抗反射涂层。异质结双极晶体管还包括位于第一和第二间隔物之间的发射器窗口，其中发射器窗口由基底的顶表面，第一和第二间隔物，中间氧化物层，非晶层和防反射涂层。异质结双极晶体管还可以包括位于发射器窗口中的发射器。

8. 发明授权

US06894328B2 Self-aligned bipolar transistor having recessed spacers and method for fabricating same 有权
标题翻译：具有凹陷垫片的自对准双极晶体管及其制造方法
公开(公告)号：US06894328B2
公开(公告)日：2005-05-17
申请号：US10442492
申请日：2003-05-21
申请人： Amol Kalburge , Kevin Q. Yin
发明人： Amol Kalburge , Kevin Q. Yin
IPC分类号： H01L21/331 , H01L29/08 , H01L29/80 , H01L31/112
CPC分类号： H01L29/66272 , H01L29/0804 , H01L29/66242 , H01L29/66287
摘要： According to one exemplary embodiment, a bipolar transistor includes a base having a top surface. The bipolar transistor further includes a first link spacer and a second link spacer situated on the top surface of the base. The bipolar transistor further includes a sacrificial post situated between the first and second link spacers, where the first and second link spacers have a height that is substantially less than a height of the sacrificial post. The bipolar transistor also includes a conformal layer situated over the sacrificial post and the first and second link spacers. According to this exemplary embodiment, the bipolar transistor further includes a sacrificial planarizing layer situated over the conformal layer, the first and second link spacers, the sacrificial post, and the base. The sacrificial planarizing layer may include, for example, an organic material such as an organic BARC (“bottom anti-reflective coating”).
摘要翻译：根据一个示例性实施例，双极晶体管包括具有顶表面的基座。双极晶体管还包括第一连接间隔物和位于基底顶表面上的第二连接间隔物。双极晶体管还包括位于第一和第二连接间隔件之间的牺牲柱，其中第一和第二连接间隔件的高度实质上小于牺牲柱的高度。双极晶体管还包括位于牺牲柱和第一和第二连接间隔物之上的共形层。根据该示例性实施例，双极晶体管还包括位于共形层之上的牺牲平坦化层，第一和第二连接间隔件，牺牲柱和基座。牺牲平坦化层可以包括例如有机材料，例如有机BARC（“底部抗反射涂层”）。

9. 发明授权

US06765243B1 HBT having a controlled emitter window opening 有权
标题翻译： HBT具有受控的发射器窗口
公开(公告)号：US06765243B1
公开(公告)日：2004-07-20
申请号：US10265334
申请日：2002-10-04
申请人： Amol M. Kalburge , Kevin Q. Yin , Klaus F. Schuegraf
发明人： Amol M. Kalburge , Kevin Q. Yin , Klaus F. Schuegraf
IPC分类号： H01L29737
CPC分类号： H01L29/66242 , H01L29/0804
摘要： According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the top surface of the base. The heterojunction bipolar transistor further comprises an intermediate oxide layer situated on the first and second oxide spacers. The heterojunction bipolar transistor further comprises an amorphous layer situated on the intermediate oxide layer. The heterojunction bipolar transistor further comprises an antireflective coating layer on the amorphous layer. The heterojunction bipolar transistor further comprises an emitter window opening situated between the first and second spacers, where the emitter window opening is defined by the top surface of the base, the first and second spacers, the intermediate oxide layer, the amorphous layer, and the antireflective coating layer. The heterojunction bipolar transistor may further comprise an emitter situated in the emitter window opening.
摘要翻译：根据一个示例性实施例，异质结双极晶体管包括具有顶表面的基极。异质结双极晶体管还包括第一间隔物和位于基底顶表面上的第二间隔物。异质结双极晶体管还包括位于第一和第二氧化物间隔物上的中间氧化物层。异质结双极晶体管还包括位于中间氧化物层上的非晶层。异质结双极晶体管还包括在非晶层上的抗反射涂层。异质结双极晶体管还包括位于第一和第二间隔物之间的发射器窗口，其中发射器窗口由基底的顶表面，第一和第二间隔物，中间氧化物层，非晶层和防反射涂层。异质结双极晶体管还可以包括位于发射器窗口中的发射器。

10. 发明授权

US07291536B1 Fabricating a self-aligned bipolar transistor having increased manufacturability 有权
标题翻译：制造具有增加的可制造性的自对准双极晶体管
公开(公告)号：US07291536B1
公开(公告)日：2007-11-06
申请号：US11175720
申请日：2005-07-06
申请人： Amol Kalburge , Kevin Q. Yin , Kenneth Ring
发明人： Amol Kalburge , Kevin Q. Yin , Kenneth Ring
IPC分类号： H01L21/8222 , H01L27/082
CPC分类号： H01L29/66242
摘要： According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.
摘要翻译：根据一个示例性实施例，双极晶体管包括具有顶表面的基座。双极晶体管还包括位于基底的顶表面上的基底氧化物层。双极晶体管还包括位于基底氧化物层上的牺牲柱。双极晶体管还包括位于基底的牺牲柱和顶表面之上的共形层，其中共形层的密度大于基底氧化物层的密度。保形层可以是例如HDPCVD氧化物。根据该示例性实施例，双极晶体管还包括位于保形层之上的牺牲平坦化层。牺牲平坦化层在第一和第二连接间隔物之间的第一区域中具有第一厚度，在第一和第二连接间隔物的第二区域中具有第二厚度，其中第二厚度通常大于第一厚度。

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