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1. 发明授权

US06472696B1 Memory cell configuration and corresponding production process 失效
标题翻译：内存单元配置及相应的生产流程
公开(公告)号：US06472696B1
公开(公告)日：2002-10-29
申请号：US09645763
申请日：2000-08-25
申请人： Ulrich Zimmermann , Thomas Böhm , Manfred Hain , Armin Kohlhase , Yoichi Otani , Andreas Rusch , Alexander Trüby
发明人： Ulrich Zimmermann , Thomas Böhm , Manfred Hain , Armin Kohlhase , Yoichi Otani , Andreas Rusch , Alexander Trüby
IPC分类号： H01L2710
CPC分类号： H01L27/11273 , H01L27/112
摘要： The memory cell configuration has a large number of memory cells provided in a semiconductor substrate and having bit-line trenches which extend in parallel in the longitudinal direction in the main face of the semiconductor substrate, at the bottoms of which in each case a first conductive region is provided, at the peaks of which in each case a second conductive region of the same conduction type as the first conductive region is provided, and in the walls of which in each case an intermediately located channel region is 0 provided; and having word lines which extend in the transverse direction along the main face of the semiconductor substrate, through specific bit-line trenches, to activate transistors provided there. An additional dopant is introduced into the trench walls of the bit-line trenches which are located between the word lines, in order to increase the corresponding transistor turn-on voltage there to suppress leakage currents.
摘要翻译：存储单元配置具有设置在半导体衬底中的大量存储单元，并且具有在半导体衬底的主面中在纵向方向上平行延伸的位线沟槽，其底部在每种情况下都具有第一导电区域被提供，其峰值在每种情况下具有与第一导电区域相同的导电类型的第二导电区域，并且在其每一种情况下壁的中间位置的沟道区域为0; 并且具有通过特定位线沟槽沿着半导体衬底的主面在横向上延伸的字线，以激活在其中设置的晶体管。另外的掺杂剂被引入位于字线之间的位线沟槽的沟槽壁中，以便在其上增加对应的晶体管导通电压以抑制漏电流。

2. 发明授权

US06258658B1 Memory cell configuration and corresponding fabrication method 有权
标题翻译：存储单元配置及相应的制造方法
公开(公告)号：US06258658B1
公开(公告)日：2001-07-10
申请号：US09250362
申请日：1999-02-12
申请人： Thomas Böhm , Volker Weinrich , Manfred Hain , Armin Kohlhase , Yoichi Otani , Andreas Rusch , Till Schlösser
发明人： Thomas Böhm , Volker Weinrich , Manfred Hain , Armin Kohlhase , Yoichi Otani , Andreas Rusch , Till Schlösser
IPC分类号： H01L218242
CPC分类号： H01L27/10823 , H01L27/10808
摘要： The memory cell configuration has a multiplicity of preferably ferroelectric memory cells in a semiconductor substrate. Mutually parallel bit line trenches run in the longitudinal direction in the main surface of the semiconductor substrate. Bit lines are disposed in the bottoms of the trenches. Source/drain regions are formed in the crowns of the trenches. Channel regions are provided in the walls of the trenches. The channel region on a wall in each case is configured such that a drivable selection transistor of the relevant memory cell is formed there, while the channel region on the other wall is configured such that the transistor located there is closed. Insulated word lines for driving the selection transistors run in the transverse direction along the main surface of the semiconductor substrate through the bit line trenches. Insulation trenches for insulating the source/drain regions in the longitudinal direction of neighboring memory cells run in the transverse direction in the main surface of the semiconductor substrate. A respective, preferably ferroelectric, capacitor is connected to the source/drain region of the respective memory cell and is arranged above the word lines.
摘要翻译：存储单元配置在半导体衬底中具有多个优选铁电存储单元。相互并行的位线沟槽在半导体衬底的主表面中沿纵向延伸。位线设置在沟槽的底部。源极/漏极区域形成在沟槽的冠部中。通道区域设置在沟槽的壁中。在每种情况下，壁上的沟道区域被构造成使得相关存储单元的可驱动选择晶体管形成在其中，而另一壁上的沟道区域被配置为使得位于那里的晶体管闭合。用于驱动选择晶体管的绝缘字线通过位线沟槽沿着半导体衬底的主表面在横向方向上延伸。用于绝缘沟槽，用于使相邻存储单元的纵向上的源极/漏极区域绝缘，在半导体衬底的主表面中沿横向延伸。相应的优选铁电电容器连接到相应存储单元的源极/漏极区域并且被布置在字线之上。

3. 发明授权

US06271074B1 Process for producing an integrated semiconductor circuit 有权
标题翻译：用于制造集成半导体电路的工艺
公开(公告)号：US06271074B1
公开(公告)日：2001-08-07
申请号：US09168909
申请日：1998-10-08
申请人： Manfred Hain , Elisabeth Fischer
发明人： Manfred Hain , Elisabeth Fischer
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L27/0805
摘要： An integrated semiconductor circuit, such as an A/D converter, includes a first zone having capacitors disposed therein. The capacitors have capacitor plates being formed of a first conductive layer and a second conductive layer. A second zone has circuit elements disposed therein. A planarizing layer and a cover layer insulate the first and second conductive layers from one another in the second zone, except for a possible peripheral region. A dielectric is formed only of the cover layer between the capacitor plates in the first zone, except for a possible peripheral region. A process for producing an integrated semiconductor circuit includes producing the first conductive layer; applying an insulating planarizing layer after producing the first conductive layer; removing the planarizing layer in the first zone until a surface of the first conductive layer is exposed, except for a possible peripheral region; applying an insulating cover layer over the entire surface; and producing the second conductive layer.
摘要翻译：诸如A / D转换器的集成半导体电路包括其中设置有电容器的第一区域。电容器具有由第一导电层和第二导电层形成的电容器板。第二区具有设置在其中的电路元件。除了可能的外围区域之外，平坦化层和覆盖层在第二区域中将第一和第二导电层彼此绝缘。除了可能的周边区域之外，电介质仅由第一区域中的电容器板之间的覆盖层形成。一种用于制造集成半导体电路的方法包括制造第一导电层; 在制造第一导电层之后施加绝缘平坦化层; 除去第一区域中的平坦化层直到暴露第一导电层的表面，除了可能的周边区域; 在整个表面上施加绝缘覆盖层; 并产生第二导电层。

4. 发明授权

US5844302A Integrated semiconductor circuit with capacitors of precisely defined capacitance and process for producing the circuit 失效
标题翻译：具有精确限定电容的电容器的集成半导体电路和用于产生电路的工艺
公开(公告)号：US5844302A
公开(公告)日：1998-12-01
申请号：US847867
申请日：1997-04-28
申请人： Manfred Hain , Elisabeth Fischer
发明人： Manfred Hain , Elisabeth Fischer
IPC分类号： H01L21/02 , H01L27/08 , H01L29/00
CPC分类号： H01L28/40 , H01L27/0805
摘要： An integrated semiconductor circuit, such as an A/D converter, includes a first zone having capacitors disposed therein. The capacitors have capacitor plates being formed of a first conductive layer and a second conductive layer. A second zone has circuit elements disposed therein. A planarizing layer and a cover layer insulate the first and second conductive layers from one another in the second zone, except for a possible peripheral region. A dielectric is formed only of the cover layer between the capacitor plates in the first zone, except for a possible peripheral region. A process for producing an integrated semiconductor circuit includes producing the first conductive layer; applying an insulating planarizing layer after producing the first conductive layer; removing the planarizing layer in the first zone until a surface of the first conductive layer is exposed, except for a possible peripheral region; applying an insulating cover layer over the entire surface; and producing the second conductive layer.
摘要翻译：诸如A / D转换器的集成半导体电路包括其中设置有电容器的第一区域。电容器具有由第一导电层和第二导电层形成的电容器板。第二区具有设置在其中的电路元件。除了可能的外围区域之外，平坦化层和覆盖层在第二区域中将第一和第二导电层彼此绝缘。除了可能的周边区域之外，电介质仅由第一区域中的电容器板之间的覆盖层形成。一种用于制造集成半导体电路的方法包括制造第一导电层; 在制造第一导电层之后施加绝缘平坦化层; 除去第一区域中的平坦化层直到暴露第一导电层的表面，除了可能的周边区域; 在整个表面上施加绝缘覆盖层; 并产生第二导电层。

5. 发明授权

US5480051A Method for the anisotropic etching of an aluminiferous layer 失效
标题翻译：含铝层的各向异性蚀刻方法
公开(公告)号：US5480051A
公开(公告)日：1996-01-02
申请号：US235987
申请日：1994-05-02
申请人： Manfred Hain
发明人： Manfred Hain
IPC分类号： C23F4/00 , H01L21/3213 , H01L21/768 , C23F1/00
CPC分类号： H01L21/76838 , C23F4/00 , H01L21/32136
摘要： Aluminiferous structures having a sidewall angle greater than or equal to zero are produced by the addition of a volatile hydrocarbon to the etching gas mixture in a plasma etching process. The volatile hydrocarbon promotes the sidewall passivation, so that extremely fine structures can be anisotropically etched. Given aluminum-copper alloys, moreover, the formation of etching residues that contain copper and are not easily volatilized is also prevented.
摘要翻译：通过在等离子体蚀刻工艺中将蚀刻气体混合物中添加挥发性烃来产生侧壁角大于或等于零的铝结构。挥发性烃促进侧壁钝化，使得极细的结构可被各向异性地蚀刻。此外，给定铝 - 铜合金，也防止了含有铜并且不容易挥发的蚀刻残留物的形成。

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