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1. 发明授权

US5388240A DRAM chip and decoding arrangement and method for cache fills 失效
标题翻译： DRAM芯片和缓存填充的解码布置和方法
公开(公告)号：US5388240A
公开(公告)日：1995-02-07
申请号：US751495
申请日：1991-08-29
申请人： Ulrich Olderdissen , Manfred Walz
发明人： Ulrich Olderdissen , Manfred Walz
IPC分类号： G06F12/04 , G06F12/0855 , G06F12/0879 , G06F12/00 , G06F12/06 , G06F13/00 , G06F13/23
CPC分类号： G06F12/0879 , G06F12/04 , G06F12/0859
摘要： A data mechanism having a random access memory (RAM) which has a plurality of groups of memory chips, each group being divisible into two equally sized chip sets. Each group of memory chips is addressed by a first address and each individual memory chip is addressed by a second address. The random access memory contains stored data. A cache, connected to the RAM, stores a portion of data stored in the RAM and is accessed by a cache address for separately reading requested data therefrom. The cache provides a cache miss signal when it does not contain the requested data. A CPU, connected to the cache and the RAM, receives the cache miss signal and provides responsive thereto, a starting address to the random access memory for starting a block transfer from the random access memory to the cache in two shots. The starting address includes the first address and the second address. The starting address identifies the group and individual chip within the group which contains the first bit which, when attempted to be read from the cache, caused the cache miss signal. A decoder, connected to the CPU and the random access memory, receives the starting address from the CPU and enables a first block data transfer from a first chip set in a first shot of the two shots starting from said first bit which caused the cache miss signal, and further enables a second block data transfer from a second chip set in a second of the shots.
摘要翻译：一种具有随机存取存储器（RAM）的数据机制，其具有多组存储器芯片，每组可分为两个相同大小的芯片组。每组存储器芯片由第一地址寻址，并且每个单独的存储器芯片由第二地址寻址。随机存取存储器包含存储的数据。连接到RAM的高速缓存存储存储在RAM中的数据的一部分，并由高速缓存地址访问，用于分别读取所请求的数据。当高速缓存未包含请求的数据时，缓存提供高速缓存未命中信号。连接到高速缓存和RAM的CPU接收高速缓存未命中信号，并向其提供起始地址到随机存取存储器，用于在两次镜头中开始从随机存取存储器到高速缓冲存储器的块传送。起始地址包括第一个地址和第二个地址。起始地址标识组内包含第一位的组和单独芯片，当尝试从高速缓存读取时，导致高速缓存未命中信号。连接到CPU和随机存取存储器的解码器从CPU接收起始地址，并且使得能够从所述第一位开始的第一个芯片组中的第一个芯片组中的第一个块数据传输，从导致高速缓存未命中的所述第一个位信号，并且还使得能够从第二芯片组中的第二个芯片组中的第二块数据传输。

2. 发明授权

US4556977A Decoding of BCH double error correction - triple error detection (DEC-TED) codes 失效
标题翻译： BCH双纠错解码 - 三重错误检测（DEC-TED）码
公开(公告)号：US4556977A
公开(公告)日：1985-12-03
申请号：US532639
申请日：1983-09-15
申请人： Ulrich Olderdissen , Hans Schumacher
发明人： Ulrich Olderdissen , Hans Schumacher
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H03M13/15 , H03M13/152 , H03M13/1575
摘要： Decoding of BCH multiple error correction code codewords with .alpha. as a primitive element of the finite field GF (2.sup.m) is accomplished by generating syndrome subvectors S.sub.1 from all column m-tuple .alpha..sup.k positions and syndrome subvectors S.sub.2 from all column m-tuple .alpha..sup.3K positions, generating a permutation of syndrome subvector S.sub.1 for each bit position on the codeword and then selecting those bit positions K where S.sub.1.sup.3 +S.sub.2 +QK=0 as the bit or bits in error.
摘要翻译：利用α作为有限域GF（2m）的原始元素的BCH多重纠错码码字的解码是通过从所有列m元组αk位置和所有列m元组α3K的综合子子向量S2生成校正子子向量S1来实现的位置，对码字上的每个比特位置产生校正子子矢量S1的置换，然后选择那些位置K，其中S13 + S2 + QK = 0作为错误的比特。

3. 发明授权

US4204634A Storing partial words in memory 失效
标题翻译：将部分单词存储在内存中
公开(公告)号：US4204634A
公开(公告)日：1980-05-27
申请号：US939314
申请日：1978-09-05
申请人： Horst E. Barsuhn , Ulrich Olderdissen , Werner Schmidt
发明人： Horst E. Barsuhn , Ulrich Olderdissen , Werner Schmidt
IPC分类号： G06F11/10 , G06F12/04 , G06F12/16 , G11C7/00 , G06F11/12
CPC分类号： G06F11/1056
摘要： This specification describes transferring a partial block of data with first and last words that are partial words from a processor and storing it in a memory protected by an error correcting code that requires the words to be stored in the memory as whole words. Prior to the initiation of the transferring and storage procedure, the memory is accessed and data words corresponding to the partial words in the partial block of data are fetched and placed in registers. Thereafter, during the transferring of the partial words, the fetched words are combined with the partial words to generate full words. Error correction check bits are added to these generated full words and the combination is stored into the memory.
摘要翻译：本说明书描述了将来自处理器的作为部分字的第一个和最后一个字的一部分数据块传送到存储在由存储在存储器中的单词作为整个字的纠错码保护的存储器中的存储器中。在传输和存储过程开始之前，访问存储器，并且获取与部分数据块中的部分字对应的数据字并将其放置在寄存器中。此后，在部分单词的传送期间，将获取的单词与部分单词组合以产生全词。纠错校验位被添加到这些生成的全部单词中，并将该组合存储到存储器中。

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