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1. 发明申请

US20100061140A1 INTEGRATED CIRCUIT INCLUDING DOPED SEMICONDUCTOR LINE HAVING CONDUCTIVE CLADDING 失效
标题翻译：集成电路，包括具有导电封接的二极管半导体线
公开(公告)号：US20100061140A1
公开(公告)日：2010-03-11
申请号：US12206439
申请日：2008-09-08
申请人： Ulrich Klostermann , Ulrike Gruening-von Schwerin , Franz Kreupl
发明人： Ulrich Klostermann , Ulrike Gruening-von Schwerin , Franz Kreupl
IPC分类号： H01L45/00 , G11C11/00 , H01L21/20
CPC分类号： H01L27/2409 , G11C13/0004 , G11C2213/72 , H01L45/06
摘要： An integrated circuit includes an array of memory cells. Each memory cell includes a diode. The integrated circuit includes a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of diodes. The integrated circuit includes conductive cladding contacting the doped semiconductor line.
摘要翻译：集成电路包括存储单元阵列。每个存储单元包括一个二极管。集成电路包括形成在半导体衬底中的掺杂半导体线。掺杂半导体线耦合到一排二极管。集成电路包括与掺杂半导体线接触的导电包层。

2. 发明授权

US08254166B2 Integrated circuit including doped semiconductor line having conductive cladding 失效
标题翻译：集成电路包括具有导电包层的掺杂半导体线
公开(公告)号：US08254166B2
公开(公告)日：2012-08-28
申请号：US12206439
申请日：2008-09-08
申请人： Ulrich Klosterman , Ulrike Gruening-von Schwerin , Franz Kreupl
发明人： Ulrich Klosterman , Ulrike Gruening-von Schwerin , Franz Kreupl
IPC分类号： G11C11/36 , H01L21/441
CPC分类号： H01L27/2409 , G11C13/0004 , G11C2213/72 , H01L45/06
摘要： An integrated circuit includes an array of memory cells. Each memory cell includes a diode. The integrated circuit includes a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of diodes. The integrated circuit includes conductive cladding contacting the doped semiconductor line.
摘要翻译：集成电路包括存储单元阵列。每个存储单元包括一个二极管。集成电路包括形成在半导体衬底中的掺杂半导体线。掺杂半导体线耦合到一排二极管。集成电路包括与掺杂半导体线接触的导电包层。

3. 发明申请

US20100027325A1 INTEGRATED CIRCUIT INCLUDING AN ARRAY OF MEMORY CELLS AND METHOD 有权
标题翻译：集成电路，包括记忆细胞阵列和方法
公开(公告)号：US20100027325A1
公开(公告)日：2010-02-04
申请号：US12182698
申请日：2008-07-30
申请人： Ulrike Gruening-von Schwerin , Lothar Risch , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Lothar Risch , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
IPC分类号： G11C11/00 , H01L21/00 , G11C11/34
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/24
摘要： An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.
摘要翻译：一种包括存储单元阵列和方法的集成电路。在一个实施例中，每个存储单元包括电阻切换存储器元件和用于从多个存储器单元中选择一个单元的选择二极管。存储元件与其顶部耦合到第一选择线并且其底侧连接到选择二极管，二极管还耦合到第二选择线的底侧。

4. 发明授权

US07601995B2 Integrated circuit having resistive memory cells 失效
标题翻译：具有电阻存储单元的集成电路
公开(公告)号：US07601995B2
公开(公告)日：2009-10-13
申请号：US11348640
申请日：2006-02-07
申请人： Thomas Happ , Ulrike Gruening-von Schwerin , Jan Boris Philipp
发明人： Thomas Happ , Ulrike Gruening-von Schwerin , Jan Boris Philipp
IPC分类号： H01L29/76
CPC分类号： H01L45/06 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L45/1226 , H01L45/1233 , H01L45/128 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L2924/0002 , H01L2924/00
摘要： A memory includes an array of memory cells, each memory cell including resistive material, a first insulation material laterally surrounding the resistive material of each memory cell, and a heat spreader between the memory cells to thermally isolate each memory cell.
摘要翻译：存储器包括存储器单元的阵列，每个存储单元包括电阻材料，横向围绕每个存储单元的电阻材料的第一绝缘材料，以及存储单元之间的散热器以热隔离每个存储单元。

5. 发明申请

US20080182378A1 METHOD OF PRODUCING AN INTEGRATED CIRCUIT HAVING A CAPACITOR 失效
标题翻译：生产具有电容器的集成电路的方法
公开(公告)号：US20080182378A1
公开(公告)日：2008-07-31
申请号：US11669613
申请日：2007-01-31
申请人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
发明人： Ulrike Gruening-von Schwerin , Rolf Weis , Wolfgang Henke , Odo Wunnicke , Till Schloesser , Florian Schnabel , Wolfgang Mueller
IPC分类号： H01L21/20
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.
摘要翻译：公开了一种形成具有电容器的集成电路的方法。在一个实施例中，该方法包括形成具有第一电极，电介质层和第二电极的电容器元件。电容器元件使用支撑层形成。

6. 发明申请

US20080142778A1 INTEGRATED CIRCUIT INCLUDING A MEMORY FABRICATED USING SELF-ALIGNED PROCESSING 有权
标题翻译：集成电路，包括使用自对准处理制成的存储器
公开(公告)号：US20080142778A1
公开(公告)日：2008-06-19
申请号：US12020988
申请日：2008-01-28
申请人： Ulrike Gruening-von Schwerin , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Thomas Happ
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/148 , H01L45/1675
摘要： An integrated circuit includes transistors in rows and columns providing an array, conductive lines in columns across the array, and resistivity changing material elements contacting the conductive lines and self-aligned to the conductive lines. The integrated circuit includes electrodes contacting the resistivity changing material elements, each electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.
摘要翻译：集成电路包括提供阵列的行和列的晶体管，跨阵列的列中的导电线以及与导电线接触并与导电线自对准的电阻率变化材料元件。集成电路包括与电阻率变化材料元件接触的电极，每个电极与导电线自对准并且耦合到晶体管的源极 - 漏极路径的一侧。

7. 发明申请

US20080049486A1 TRANSISTOR, MEMORY CELL ARRAY AND METHOD FOR FORMING AND OPERATING A MEMORY DEVICE 失效
标题翻译：晶体管，存储单元阵列和形成和操作存储器件的方法
公开(公告)号：US20080049486A1
公开(公告)日：2008-02-28
申请号：US11467747
申请日：2006-08-28
申请人： Ulrike Gruening-von Schwerin
发明人： Ulrike Gruening-von Schwerin
IPC分类号： G11C17/00 , H01L29/94 , H01L21/8238
CPC分类号： H01L27/105 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C2213/79 , H01L27/1052 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A substrate forming an array of vertical transistor cells for selecting one of a plurality of memory cells and wherein each memory cell couples a transistor to a bit line via a memory element and is addressable by selecting two word lines and a bit line is disclosed. For minimizing the area of a cell and reducing complexity in production, one word line trench takes one word line, wherein in a first embodiment a first word line in a first word line trench forms a plurality of gate electrodes on one sidewall of active areas of a first and a second, adjacent row of transistor cells in word line direction, and wherein a second word line in an adjacent word line trench forms a plurality of gate electrodes on the opposite sidewall of active areas of the second and of a third row of transistor cells in wordline direction.
摘要翻译：一种形成用于选择多个存储单元之一的垂直晶体管单元阵列的衬底，其中每个存储单元经由存储器元件将晶体管耦合到位线，并且可通过选择两条字线进行寻址，并且公开了位线。为了最小化单元的面积并降低生产的复杂性，一个字线沟槽占用一个字线，其中在第一实施例中，第一字线沟槽中的第一字线在多个栅电极的有效区域的一个侧壁上形成多个栅电极第一和第二相邻行的晶体管单元，并且其中相邻字线沟槽中的第二字线在第二行和第三行的有效区域的相对侧壁上形成多个栅电极晶体管单元在字线方向。

8. 发明授权

US07324365B2 Phase change memory fabricated using self-aligned processing 有权
标题翻译：使用自对准处理制造的相变存储器
公开(公告)号：US07324365B2
公开(公告)日：2008-01-29
申请号：US11366370
申请日：2006-03-02
申请人： Ulrike Gruening-von Schwerin , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Thomas Happ
IPC分类号： G11C11/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/148 , H01L45/1675
摘要： A memory includes transistors in rows and columns providing an array, conductive lines in columns across the array, and phase change elements contacting the conductive lines and self-aligned to the conductive lines. The memory includes bottom electrodes contacting the phase change elements, each bottom electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.
摘要翻译：存储器包括行和列中提供阵列的晶体管，跨阵列的列中的导线以及接触导线并与导线自对准的相变元件。存储器包括接触相变元件的底部电极，每个底部电极与导电线自对准并且耦合到晶体管的源极 - 漏极通路的一侧。

9. 发明申请

US20070181932A1 Thermal isolation of phase change memory cells 有权
标题翻译：相变记忆体的热隔离
公开(公告)号：US20070181932A1
公开(公告)日：2007-08-09
申请号：US11437211
申请日：2006-05-19
申请人： Thomas Happ , Jan Philipp , Ulrike Gruening-von Schwerin
发明人： Thomas Happ , Jan Philipp , Ulrike Gruening-von Schwerin
IPC分类号： H01L29/76
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/128 , H01L45/1293 , H01L45/148
摘要： A memory includes an array of resistive memory cells, bit lines between rows of the memory cells for accessing the memory cells, and a conductive plate coupled to each of the memory cells.
摘要翻译：存储器包括电阻存储器单元的阵列，用于存储单元的存储单元的行之间的位线以及耦合到每个存储单元的导电板。

10. 发明申请

US20070096182A1 TRANSISTOR, MEOMORY CELL ARRAY AND METHOD OF MANUFACTURING A TRANSISTOR 审中-公开
标题翻译：晶体管，晶体管阵列和制造晶体管的方法
公开(公告)号：US20070096182A1
公开(公告)日：2007-05-03
申请号：US11556897
申请日：2006-11-06
申请人： Till Schloesser , Rolf Weis , Ulrike Gruening-von Schwerin
发明人： Till Schloesser , Rolf Weis , Ulrike Gruening-von Schwerin
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： G11C11/404 , H01L27/0207 , H01L27/10873 , H01L27/10879 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7854
摘要： A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically isolated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.
摘要翻译：公开了晶体管，存储单元阵列和制造晶体管的方法。在一个实施例中，本发明涉及至少部分地形成在半导体衬底中的晶体管，包括第一和第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域，所述沟道区域是设置在所述半导体衬底中，以及栅电极，沿着所述沟道区设置并与所述沟道区电隔离，用于控制在所述第一和第二源/漏区之间流动的电流，其中所述沟道区包括所述通道具有脊的形状，所述脊包括垂直于连接所述第一和第二源极/漏极区的线的横截面中的顶侧和两个侧边，其中所述顶侧设置在所述半导体的表面下方基板和所述栅电极沿着所述顶侧和所述两个横向侧面设置。

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