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1. 发明申请

US20090254732A1 Enabling Memory Module Slots In A Computing System After A Repair Action 有权
标题翻译：维修行动后，在计算系统中启用内存模块插槽
公开(公告)号：US20090254732A1
公开(公告)日：2009-10-08
申请号：US11960544
申请日：2008-04-08
申请人： Tu T. Dang , Robert F. Kantner, JR. , Henry G. McMillan , Carl A. Morrell , Challis L. Purrington , Mark W. Williams
发明人： Tu T. Dang , Robert F. Kantner, JR. , Henry G. McMillan , Carl A. Morrell , Challis L. Purrington , Mark W. Williams
IPC分类号： G06F12/00
CPC分类号： G06F13/409 , G06F11/006 , G06F11/073 , G06F11/0793
摘要： Methods, systems, and products are disclosed for enabling memory module slots in a computing system after a repair action, the computing system having a plurality of memory module slots and having at least one memory module installed in one of the memory module slots, that includes: determining, during a boot process for the computing system, whether any of the memory module slots are disabled; and if any of the memory module slots are disabled: retrieving, for each memory module installed in one of the memory module slots, a memory module identifier for that memory module, retrieving, from non-volatile memory of the computing system, previously stored memory module identifiers, determining whether the retrieved memory module identifiers match the previously stored memory module identifiers, and enabling the disabled memory module slots if the retrieved memory module identifiers do not match the previously stored memory module identifiers.
摘要翻译：公开了方法，系统和产品，用于在修复动作之后使计算系统中的存储器模块插槽能够启动，所述计算系统具有多个存储器模块插槽，并且具有安装在存储器模块插槽之一中的至少一个存储器模块，：在所述计算系统的引导过程期间确定是否禁用所述存储器模块插槽; 并且如果任何一个存储器模块插槽被禁用：对于安装在其中一个存储器模块插槽中的每个存储器模块，检索该存储器模块的存储器模块标识符，从计算系统的非易失性存储器检索先前存储的存储器模块标识符，确定所检索的存储器模块标识符是否与先前存储的存储器模块标识符匹配，以及如果所检索的存储器模块标识符与先前存储的存储器模块标识符不匹配，则启用禁用的存储器模块插槽。

2. 发明授权

US08006028B2 Enabling memory module slots in a computing system after a repair action 有权
标题翻译：在修复操作后，在计算系统中启用内存模块插槽
公开(公告)号：US08006028B2
公开(公告)日：2011-08-23
申请号：US11960544
申请日：2008-04-08
申请人： Tu T. Dang , Robert F. Kantner, Jr. , Henry G. McMillan , Carl A. Morrell , Challis L. Purrington , Mark W. Williams
发明人： Tu T. Dang , Robert F. Kantner, Jr. , Henry G. McMillan , Carl A. Morrell , Challis L. Purrington , Mark W. Williams
IPC分类号： G06F12/00
CPC分类号： G06F13/409 , G06F11/006 , G06F11/073 , G06F11/0793
摘要： Methods, systems, and products are disclosed for enabling memory module slots in a computing system after a repair action, the computing system having a plurality of memory module slots and having at least one memory module installed in one of the memory module slots, that includes: determining, during a boot process for the computing system, whether any of the memory module slots are disabled; and if any of the memory module slots are disabled: retrieving, for each memory module installed in one of the memory module slots, a memory module identifier for that memory module, retrieving, from non-volatile memory of the computing system, previously stored memory module identifiers, determining whether the retrieved memory module identifiers match the previously stored memory module identifiers, and enabling the disabled memory module slots if the retrieved memory module identifiers do not match the previously stored memory module identifiers.
摘要翻译：公开了方法，系统和产品，用于在修复动作之后使计算系统中的存储器模块插槽能够启动，所述计算系统具有多个存储器模块插槽，并且具有安装在存储器模块插槽之一中的至少一个存储器模块，：在所述计算系统的引导过程期间确定是否禁用所述存储器模块插槽; 并且如果任何一个存储器模块插槽被禁用：对于安装在其中一个存储器模块插槽中的每个存储器模块，检索该存储器模块的存储器模块标识符，从计算系统的非易失性存储器检索先前存储的存储器模块标识符，确定所检索的存储器模块标识符是否与先前存储的存储器模块标识符匹配，以及如果所检索的存储器模块标识符与先前存储的存储器模块标识符不匹配，则启用禁用的存储器模块插槽。

3. 发明授权

US07954007B2 Detecting faulty CPU heat sink coupling during system power-up 失效
标题翻译：在系统上电期间检测CPU散热器耦合故障
公开(公告)号：US07954007B2
公开(公告)日：2011-05-31
申请号：US11551961
申请日：2006-10-23
申请人： Henry G. McMillan , Christopher C. Moody , Challis L. Purrington , Terry L. Sawyers , Michael L. Scollard , Richard P. Southers , Troy S. Voytko , Christopher C. West , Christopher L. Wood
发明人： Henry G. McMillan , Christopher C. Moody , Challis L. Purrington , Terry L. Sawyers , Michael L. Scollard , Richard P. Southers , Troy S. Voytko , Christopher C. West , Christopher L. Wood
IPC分类号： G06F11/00
CPC分类号： H01L23/34 , G06F1/206 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to the detection of faulty CPU heat sink coupling during system power-up. A method in accordance with an embodiment of the present invention includes: monitoring a slope of a CPU temperature rise from initial system power-up; determining if the slope of the CPU temperature rise exceeds an expected value; and in the case that the slope of the CPU temperature rise exceeds the expected value, indicating an existence of a possible fault (PFA) related to a heat sink coupled to the CPU.
摘要翻译：本发明涉及在系统上电期间检测故障的CPU散热器耦合。根据本发明的实施例的方法包括：从初始系统上电监视CPU温度上升的斜率; 确定CPU温度上升的斜率是否超过预期值; 并且在CPU温度升高的斜率超过预期值的情况下，指示与耦合到CPU的散热器相关的可能故障（PFA）的存在。

4. 发明申请

US20080154536A1 DETECTING FAULTY CPU HEAT SINK COUPLING DURING SYSTEM POWER-UP 失效
标题翻译：在系统加电期间检测故障CPU散热耦合
公开(公告)号：US20080154536A1
公开(公告)日：2008-06-26
申请号：US11551961
申请日：2006-10-23
申请人： Henry G. McMillan , Christopher C. Moody , Challis L. Purrington , Terry L. Sawyers , Michael L. Scollard , Richard P. Southers , Troy S. Voytko , Christopher C. West , Christopher L. Wood
发明人： Henry G. McMillan , Christopher C. Moody , Challis L. Purrington , Terry L. Sawyers , Michael L. Scollard , Richard P. Southers , Troy S. Voytko , Christopher C. West , Christopher L. Wood
IPC分类号： G06F15/00
CPC分类号： H01L23/34 , G06F1/206 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to the detection of faulty CPU heat sink coupling during system power-up. A method in accordance with an embodiment of the present invention includes: monitoring a slope of a CPU temperature rise from initial system power-up; determining if the slope of the CPU temperature rise exceeds an expected value; and in the case that the slope of the CPU temperature rise exceeds the expected value, indicating an existence of a possible fault (PFA) related to a heat sink coupled to the CPU.
摘要翻译：本发明涉及在系统上电期间检测故障的CPU散热器耦合。根据本发明的实施例的方法包括：从初始系统上电监视CPU温度上升的斜率; 确定CPU温度上升的斜率是否超过预期值; 并且在CPU温度升高的斜率超过预期值的情况下，指示与耦合到CPU的散热器相关的可能故障（PFA）的存在。

5. 发明授权

US07654840B1 DIMM connector and memory system with compensated airflow impedance 有权
标题翻译： DIMM连接器和具有补偿气流阻抗的存储器系统
公开(公告)号：US07654840B1
公开(公告)日：2010-02-02
申请号：US12398289
申请日：2009-03-05
申请人： Ivan R. Zapata , Victor A. Stankevich , Challis L. Purrington , Henry G. McMillan , Brian A. Baker
发明人： Ivan R. Zapata , Victor A. Stankevich , Challis L. Purrington , Henry G. McMillan , Brian A. Baker
IPC分类号： H01R4/60
CPC分类号： H01R13/62988 , H01R12/721
摘要： An embodiment of the present invention is directed to a memory module connector having a pivotable air baffle that controls airflow at the memory module connector. When the memory module connector is occupied by a memory module, the air baffle may rest on an upper edge of the memory module, substantially parallel to the system board and in general alignment with the airflow. When the memory module has been removed, the air baffle may be pivoted downward toward the connector base and into the airflow, to offset the reduction in airflow impedance caused by the removal of the memory module from the memory module connector.
摘要翻译：本发明的一个实施例涉及一种存储器模块连接器，其具有控制存储器模块连接器上的气流的可枢转空气挡板。当存储器模块连接器被存储器模块占用时，空气挡板可以搁置在存储器模块的上边缘上，基本上平行于系统板并且与气流大致对准。当存储器模块已经被移除时，空气挡板可以朝向连接器底座向下枢转并进入气流中，以抵消由存储器模块连接器移除存储器模块引起的气流阻抗的减小。

6. 发明授权

US07992030B2 Fall time accelerator circuit 有权
标题翻译：下降时间加速器电路
公开(公告)号：US07992030B2
公开(公告)日：2011-08-02
申请号：US11746102
申请日：2007-05-09
申请人： Henry G. McMillan , Pravin Patel , Challis L. Purrington , Gwendolyn R. Tobin , Christopher C. West , Ivan R. Zapata
发明人： Henry G. McMillan , Pravin Patel , Challis L. Purrington , Gwendolyn R. Tobin , Christopher C. West , Ivan R. Zapata
IPC分类号： G06F1/00
CPC分类号： H03K5/1534 , H03K19/01721
摘要： Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus.
摘要翻译：本发明的实施例解决了与数字信号传输相关的技术缺陷，并且提供了一种用于USB接口的新颖且不可见的下降时间加速器电路。在本发明的一个实施例中，USB接口可以包括通过USB总线耦合到主控制器驱动器的USB端口驱动器。 USB接口还可以包括在USB端口驱动器和主机控制器驱动器之间耦合到USB总线的下降时间加速器电路。下降时间加速器电路可以包括耦合到来自USB总线的入站信号路径的脉冲信号发生器，并且被布置成在检测入站信号路径上的数字信号的下降沿时产生可调脉冲。电路还可以包括另外耦合到入站信号路径的有源定时器，以将可调谐脉冲保持一段时间。最后，电路可以包括耦合到来自脉冲信号发生器的出站信号路径的下降驱动信号加强器，该脉冲信号发生器布置成将出站信号路径上的可调谐脉冲释放到USB总线上。

7. 发明授权

US07650517B2 Throttle management for blade system 有权
标题翻译：叶片系统的油门管理
公开(公告)号：US07650517B2
公开(公告)日：2010-01-19
申请号：US11311818
申请日：2005-12-19
申请人： James E. Hughes , Henry G. McMillan , Challis L. Purrington , Michael L. Scollard , Gary R. Shippy , Paul M. Smith , Maya P. Yarbrough
发明人： James E. Hughes , Henry G. McMillan , Challis L. Purrington , Michael L. Scollard , Gary R. Shippy , Paul M. Smith , Maya P. Yarbrough
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3228
摘要： Power is allocated to blades based on an estimate of the actual power they are expected to use rather than their maximum-power draw-value. To protect against situations where the estimated actual-power draw-value is exceeded, a hardware comparator monitors the blade system load against a predetermined threshold value set by a management module (MM) based on user input. If this threshold value is exceeded, a throttle latch is triggered, based on a signal from a service processor monitoring the blade system load. The output of this latch directly engages throttling. The service processor also monitors the output of the latch and communicates information regarding the throttling to the MM for evaluation.
摘要翻译：根据其预期使用的实际功率的估计而不是其最大功率抽取值，将功率分配给刀片。为了防止超过估计的实际功率抽取值的情况，硬件比较器基于由管理模块（MM）基于用户输入设置的预定阈值来监视刀片系统负载。如果超过该阈值，则根据监视刀片系统负载的服务处理器的信号触发油门闩锁。该闩锁的输出直接接合节流。服务处理器还监视锁存器的输出并将关于限流的信息传送到MM以进行评估。

8. 发明申请

US20080278207A1 FALL TIME ACCELERATOR CIRCUIT 有权
标题翻译：落地时间加速器电路
公开(公告)号：US20080278207A1
公开(公告)日：2008-11-13
申请号：US11746102
申请日：2007-05-09
申请人： Henry G. McMillan , Pravin Patel , Challis L. Purrington , Gwendolyn R. Tobin , Christopher C. West , Ivan R. Zapata
发明人： Henry G. McMillan , Pravin Patel , Challis L. Purrington , Gwendolyn R. Tobin , Christopher C. West , Ivan R. Zapata
IPC分类号： H03K5/12
CPC分类号： H03K5/1534 , H03K19/01721
摘要： Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus.
摘要翻译：本发明的实施例解决了与数字信号传输相关的技术缺陷，并且提供了一种用于USB接口的新颖且不可见的下降时间加速器电路。在本发明的一个实施例中，USB接口可以包括通过USB总线耦合到主控制器驱动器的USB端口驱动器。 USB接口还可以包括在USB端口驱动器和主机控制器驱动器之间耦合到USB总线的下降时间加速器电路。下降时间加速器电路可以包括耦合到来自USB总线的入站信号路径的脉冲信号发生器，并且被布置成在检测入站信号路径上的数字信号的下降沿时产生可调脉冲。电路还可以包括另外耦合到入站信号路径的有源定时器，以将可调谐脉冲保持一段时间。最后，电路可以包括耦合到来自脉冲信号发生器的出站信号路径的下降驱动信号加强器，该脉冲信号发生器布置成将出站信号路径上的可调谐脉冲释放到USB总线上。

9. 发明申请

US20110205769A1 POWER SHARING METHOD AND SYSTEM FOR TWO-STAGE POWER SUPPLIES 有权
标题翻译：两级电源的电源共享方法和系统
公开(公告)号：US20110205769A1
公开(公告)日：2011-08-25
申请号：US12708620
申请日：2010-02-19
申请人： Edward L. Blackwell , Nickolas J. Gruendler , Henry G. McMillan
发明人： Edward L. Blackwell , Nickolas J. Gruendler , Henry G. McMillan
IPC分类号： H02J1/10
CPC分类号： H02J1/10
摘要： One embodiment of the invention provides a method for optimizing the power consumption in a redundant power system. A pulse width modulation waveform is generated in each of a first and second power supply to control the power output of each power supply. In response to the system load reaching a power setpoint, the first and second power supplies supply power to the system load in parallel. In response to the system load being below the power setpoint, the pulse width modulation waveform is disabled or blocked in the second power supply, and the system load is powered substantially entirely with the first power supply.
摘要翻译：本发明的一个实施例提供了一种用于优化冗余电力系统中的功率消耗的方法。在第一和第二电源中的每一个中产生脉宽调制波形，以控制每个电源的功率输出。响应于系统负载达到功率设定值，第一和第二电源并行地向系统负载供电。响应于系统负载低于功率设定点，脉冲宽度调制波形在第二电源中被禁用或阻塞，并且系统负载基本上完全由第一电源供电。

10. 发明授权

US08400795B2 Power sharing method and system for two-stage power supplies 有权
标题翻译：两级电源的功率分配方法和系统
公开(公告)号：US08400795B2
公开(公告)日：2013-03-19
申请号：US12708620
申请日：2010-02-19
申请人： Edward L. Blackwell , Nickolas J. Gruendler , Henry G. McMillan
发明人： Edward L. Blackwell , Nickolas J. Gruendler , Henry G. McMillan
IPC分类号： H02M7/00
CPC分类号： H02J1/10
摘要： One embodiment of the invention provides a method for optimizing the power consumption in a redundant power system. A pulse width modulation waveform is generated in each of a first and second power supply to control the power output of each power supply. In response to the system load reaching a power setpoint, the first and second power supplies supply power to the system load in parallel. In response to the system load being below the power setpoint, the pulse width modulation waveform is disabled or blocked in the second power supply, and the system load is powered substantially entirely with the first power supply.
摘要翻译：本发明的一个实施例提供了一种用于优化冗余电力系统中的功率消耗的方法。在第一和第二电源中的每一个中产生脉宽调制波形，以控制每个电源的功率输出。响应于系统负载达到功率设定值，第一和第二电源并行地向系统负载供电。响应于系统负载低于功率设定点，脉冲宽度调制波形在第二电源中被禁用或阻塞，并且系统负载基本上完全由第一电源供电。

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