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1. 发明授权

US07977800B2 Semiconductor device and fabrication method for the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07977800B2
公开(公告)日：2011-07-12
申请号：US12247518
申请日：2008-10-08
申请人： Tsutomu Oosuka , Hisashi Ogawa , Yoshihiro Sato
发明人： Tsutomu Oosuka , Hisashi Ogawa , Yoshihiro Sato
IPC分类号： H01L21/8234
CPC分类号： H01L23/535 , H01L21/28518 , H01L21/28525 , H01L21/76895 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L27/11 , H01L29/161 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
摘要翻译：半导体器件包括：晶体管，其具有形成在半导体衬底上的栅极电极和形成在半导体衬底的位于栅电极两侧的部分中的第一和第二源极/漏极区域; 形成在相对于第一源极/漏极区域的与栅电极相对的位置处的栅极互连; 以及形成在所述第一源极/漏极区域上以在所述半导体衬底的顶表面上方突出的第一硅 - 锗层。栅极互连和第一源极/漏极区域经由包括第一硅 - 锗层的局部互连结构连接。

2. 发明申请

US20110227168A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110227168A1
公开(公告)日：2011-09-22
申请号：US13149554
申请日：2011-05-31
申请人： Tsutomu Oosuka , Hisashi Ogawa , Yoshihiro Sato
发明人： Tsutomu Oosuka , Hisashi Ogawa , Yoshihiro Sato
IPC分类号： H01L29/78
CPC分类号： H01L23/535 , H01L21/28518 , H01L21/28525 , H01L21/76895 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L27/11 , H01L29/161 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
摘要翻译：半导体器件包括：晶体管，其具有形成在半导体衬底上的栅极电极和形成在半导体衬底的位于栅电极两侧的部分中的第一和第二源极/漏极区域; 形成在相对于第一源极/漏极区域的与栅电极相对的位置处的栅极互连; 以及形成在所述第一源极/漏极区域上以在所述半导体衬底的顶表面上方突出的第一硅 - 锗层。栅极互连和第一源极/漏极区域经由包括第一硅 - 锗层的局部互连结构连接。

3. 发明申请

US20100059827A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100059827A1
公开(公告)日：2010-03-11
申请号：US12619222
申请日：2009-11-16
申请人： Tsutomu OOSUKA , Yoshihiro Sato , Hisashi Ogawa
发明人： Tsutomu OOSUKA , Yoshihiro Sato , Hisashi Ogawa
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/82345 , H01L21/823462 , H01L21/823481 , H01L21/823857 , H01L21/823878
摘要： A first and second gate electrodes are formed on a first and second active regions, respectively. The first and second gate electrodes have a first and second metal-containing conductive films, respectively. The first and second metal-containing conductive films are formed on the isolation region for segmenting the first and second active regions to be spaced apart from each other. A third metal-containing conductive film, which is a part of each of the first and second gate electrodes, is continuously formed from a top of the first metal-containing conductive film through a top of the isolation region to a top of the second metal-containing conductive film. The third metal-containing conductive film is in contact with the first and second metal-containing conductive films.
摘要翻译：第一和第二栅电极分别形成在第一和第二有源区上。第一和第二栅电极分别具有第一和第二含金属的导电膜。第一和第二含金属导电膜形成在隔离区域上，用于将第一和第二有源区域彼此分隔开。作为第一和第二栅电极中的每一个的一部分的第三含金属导电膜从第一含金属导电膜的顶部通过隔离区的顶部连续地形成到第二金属的顶部的导电膜。第三含金属导电膜与第一和第二含金属导电膜接触。

4. 发明授权

US08350332B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08350332B2
公开(公告)日：2013-01-08
申请号：US12619222
申请日：2009-11-16
申请人： Tsutomu Oosuka , Yoshihiro Sato , Hisashi Ogawa
发明人： Tsutomu Oosuka , Yoshihiro Sato , Hisashi Ogawa
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/82345 , H01L21/823462 , H01L21/823481 , H01L21/823857 , H01L21/823878
摘要： A first and second gate electrodes are formed on a first and second active regions, respectively. The first and second gate electrodes have a first and second metal-containing conductive films, respectively. The first and second metal-containing conductive films are formed on the isolation region for segmenting the first and second active regions to be spaced apart from each other. A third metal-containing conductive film, which is a part of each of the first and second gate electrodes, is continuously formed from a top of the first metal-containing conductive film through a top of the isolation region to a top of the second metal-containing conductive film. The third metal-containing conductive film is in contact with the first and second metal-containing conductive films.
摘要翻译：第一和第二栅电极分别形成在第一和第二有源区上。第一和第二栅电极分别具有第一和第二含金属的导电膜。第一和第二含金属导电膜形成在隔离区域上，用于将第一和第二有源区域彼此分隔开。作为第一和第二栅电极中的每一个的一部分的第三含金属导电膜从第一含金属导电膜的顶部通过隔离区的顶部连续地形成到第二金属的顶部的导电膜。第三含金属导电膜与第一和第二含金属导电膜接触。

5. 发明授权

US08344455B2 Semiconductor device and fabrication method for the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US08344455B2
公开(公告)日：2013-01-01
申请号：US13149554
申请日：2011-05-31
申请人： Tsutomu Oosuka , Hisashi Ogawa , Yoshihiro Sato
发明人： Tsutomu Oosuka , Hisashi Ogawa , Yoshihiro Sato
IPC分类号： H01L29/78
CPC分类号： H01L23/535 , H01L21/28518 , H01L21/28525 , H01L21/76895 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L27/11 , H01L29/161 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
摘要翻译：半导体器件包括：晶体管，其具有形成在半导体衬底上的栅极电极和形成在半导体衬底的位于栅电极两侧的部分中的第一和第二源极/漏极区域; 形成在相对于第一源极/漏极区域的与栅电极相对的位置处的栅极互连; 以及形成在所述第一源极/漏极区域上以在所述半导体衬底的顶表面上方突出的第一硅 - 锗层。栅极互连和第一源极/漏极区域经由包括第一硅 - 锗层的局部互连结构连接。

6. 发明申请

US20100072523A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100072523A1
公开(公告)日：2010-03-25
申请号：US12629508
申请日：2009-12-02
申请人： Yoshihiro SATO , Hisashi Ogawa
发明人： Yoshihiro SATO , Hisashi Ogawa
IPC分类号： H01L27/092 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/28088 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate electrode includes a second metal film formed on a first gate insulating film, and an insulating film formed, extending over side surfaces of the first gate electrode and upper surfaces of regions located in the first active region laterally outside the first gate electrode. The second MIS transistor includes a second gate electrode including a first metal film formed on a second gate insulating film and a conductive film formed on the first metal film, and the insulating film formed, extending over side surfaces of the second gate electrode and upper surfaces of regions located in the second active region laterally outside the second gate electrode. The first and second metal films are made of different metal materials.
摘要翻译：半导体器件包括第一MIS晶体管和第二MIS晶体管。第一MIS晶体管包括：第一栅电极，包括形成在第一栅极绝缘膜上的第二金属膜和形成的绝缘膜，所述绝缘膜在第一栅电极的侧表面和位于第一有源区域的区域的上表面横向外侧延伸第一栅电极。第二MIS晶体管包括第二栅电极，其包括形成在第二栅极绝缘膜上的第一金属膜和形成在第一金属膜上的导电膜，并且形成在第二栅电极和上表面的侧表面上延伸的绝缘膜位于第二有源区中的位于第二栅电极的横向外侧的区域。第一和第二金属膜由不同的金属材料制成。

7. 发明授权

US08198686B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08198686B2
公开(公告)日：2012-06-12
申请号：US12629508
申请日：2009-12-02
申请人： Yoshihiro Sato , Hisashi Ogawa
发明人： Yoshihiro Sato , Hisashi Ogawa
IPC分类号： H01L21/70
CPC分类号： H01L21/823807 , H01L21/28088 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate electrode includes a second metal film formed on a first gate insulating film, and an insulating film formed, extending over side surfaces of the first gate electrode and upper surfaces of regions located in the first active region laterally outside the first gate electrode. The second MIS transistor includes a second gate electrode including a first metal film formed on a second gate insulating film and a conductive film formed on the first metal film, and the insulating film formed, extending over side surfaces of the second gate electrode and upper surfaces of regions located in the second active region laterally outside the second gate electrode. The first and second metal films are made of different metal materials.
摘要翻译：半导体器件包括第一MIS晶体管和第二MIS晶体管。第一MIS晶体管包括：第一栅电极，包括形成在第一栅极绝缘膜上的第二金属膜和形成的绝缘膜，所述绝缘膜在第一栅电极的侧表面和位于第一有源区域的区域的上表面横向外侧延伸第一栅电极。第二MIS晶体管包括第二栅电极，其包括形成在第二栅极绝缘膜上的第一金属膜和形成在第一金属膜上的导电膜，并且形成在第二栅电极和上表面的侧表面上延伸的绝缘膜位于第二有源区中的位于第二栅电极的横向外侧的区域。第一和第二金属膜由不同的金属材料制成。

8. 发明申请

US20070096212A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070096212A1
公开(公告)日：2007-05-03
申请号：US11583846
申请日：2006-10-20
申请人： Yoshihiro Sato , Hisashi Ogawa
发明人： Yoshihiro Sato , Hisashi Ogawa
IPC分类号： H01L27/12 , H01L21/4763 , H01L27/01 , H01L31/0392
CPC分类号： H01L21/823425 , H01L21/76895 , H01L21/823443 , H01L21/823456 , H01L21/823468 , H01L21/823475
摘要： A semiconductor device includes a fully silicided first gate interconnect formed on a semiconductor substrate, a first sidewall formed on a side of the first gate interconnect, and impurity diffusion layers formed in an active region of the semiconductor substrate. A shared contact plug is formed in an interlayer dielectric formed on the semiconductor substrate so as to be connected to the first gate interconnect and associated one of the impurity diffusion layers. The first gate interconnect is formed, at its part connected to the shared contact plug, with a projection part projecting beyond the first sidewall.
摘要翻译：半导体器件包括形成在半导体衬底上的完全硅化的第一栅极互连，形成在第一栅极互连的一侧上的第一侧壁和形成在半导体衬底的有源区中的杂质扩散层。共同的接触插塞形成在半导体衬底上形成的层间电介质中，以便连接到第一栅极互连和相关的一个杂质扩散层。第一栅极互连在其部分连接到共享的接触插塞上形成有突出超过第一侧壁的突起部分。

9. 发明申请

US20080128825A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080128825A1
公开(公告)日：2008-06-05
申请号：US11979870
申请日：2007-11-09
申请人： Yoshihiro Sato , Hisashi Ogawa
发明人： Yoshihiro Sato , Hisashi Ogawa
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/82385 , H01L21/823864 , H01L21/823871 , H01L29/4975 , H01L29/66545 , H01L29/7833
摘要： A p-type MIS transistor includes a first gate insulating film formed on a first active region; and a first fully silicided gate pattern that is obtained by fully siliciding a silicon film, is formed to extend over the first active region with the first gate insulating film sandwiched therebetween, and includes a first fully silicided gate electrode provided on the first active region and a first fully silicided gate line provided on the isolation region. The first fully silicided gate pattern includes, along a gate width direction, a portion having a first thickness and including the first fully silicided gate electrode and portions each having a second thickness larger than the first thickness and respectively disposed on both sides of the portion having the first thickness.
摘要翻译： p型MIS晶体管包括形成在第一有源区上的第一栅极绝缘膜; 并且通过使硅膜完全硅化而获得的第一完全硅化的栅极图案被形成为在第一有源区域上延伸，并且第一栅极绝缘膜夹在其间，并且包括设置在第一有源区上的第一完全硅化栅电极和设置在隔离区上的第一完全硅化栅极线。第一完全硅化的栅极图案沿着栅极宽度方向包括具有第一厚度的部分，并且包括第一完全硅化的栅极电极和各自具有大于第一厚度的第二厚度的部分，并且分别设置在具有第一厚度的部分的两侧，第一厚度。

10. 发明授权

US08018004B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08018004B2
公开(公告)日：2011-09-13
申请号：US12028601
申请日：2008-02-08
申请人： Yoshihiro Sato , Hisashi Ogawa
发明人： Yoshihiro Sato , Hisashi Ogawa
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823828 , H01L21/823835 , H01L21/823842 , H01L27/092
摘要： A semiconductor device comprises a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film formed on a first active region, and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes a second gate insulating film formed on a second active region and made of an insulating material different from that of the first gate insulating film, and a second gate electrode formed on the second gate insulating film. Upper regions of the first gate electrode and the second gate electrode are electrically connected to each other on the isolation region located between the first active region and the second active region, and lower regions thereof are separated from each other with a sidewall insulating film made of the same insulating material as that of the first gate insulating film being interposed therebetween.
摘要翻译：半导体器件包括第一MIS晶体管和第二MIS晶体管。第一MIS晶体管包括形成在第一有源区上的第一栅极绝缘膜和形成在第一栅极绝缘膜上的第一栅电极。第二MIS晶体管包括形成在第二有源区上并由与第一栅极绝缘膜的绝缘材料不同的绝缘材料制成的第二栅极绝缘膜，以及形成在第二栅极绝缘膜上的第二栅电极。第一栅极电极和第二栅电极的上部区域在位于第一有源区域和第二有源区域之间的隔离区域上彼此电连接，并且其下部区域由侧壁绝缘膜彼此分离，侧壁绝缘膜由与第一栅极绝缘膜的绝缘材料相同的绝缘材料插入其间。

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