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1. 发明申请

US20100260312A1 SHIFT REGISTER OF LCD DEVICES 有权
标题翻译： LCD设备的移位寄存器
公开(公告)号：US20100260312A1
公开(公告)日：2010-10-14
申请号：US12607042
申请日：2009-10-27
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Chun-Hsin Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Chun-Hsin Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0219 , G11C19/28
摘要： A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.
摘要翻译：移位寄存器包括串联耦合的多个移位寄存器单元。接收输入端的输入电压和输出端的输出电压的每个移位寄存器单元包括节点，上拉驱动电路，上拉电路和第一至第三下拉电路。上拉驱动电路可以将输入电压传输到节点，并且上拉电路可以基于高频时钟信号和输入信号提供输出电压。第一下拉电路可以基于第一低频时钟信号在节点处或在输出端提供偏置电压。第二下拉电路可以基于第二低频时钟信号在节点处或在输出端提供偏置电压。第三下拉电路可以基于反馈电压在节点处或输出端提供偏置电压。

2. 发明申请

US20120250816A1 SHIFT REGISTER OF LCD DEVICES 有权
标题翻译： LCD设备的移位寄存器
公开(公告)号：US20120250816A1
公开(公告)日：2012-10-04
申请号：US13492916
申请日：2012-06-10
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Chun-Hsin Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Chun-Hsin Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0219 , G11C19/28
摘要： A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.
摘要翻译：移位寄存器包括串联耦合的多个移位寄存器单元。接收输入端的输入电压和输出端的输出电压的每个移位寄存器单元包括节点，上拉驱动电路，上拉电路和第一至第三下拉电路。上拉驱动电路可以将输入电压传输到节点，并且上拉电路可以基于高频时钟信号和输入信号提供输出电压。第一下拉电路可以基于第一低频时钟信号在节点处或在输出端提供偏置电压。第二下拉电路可以基于第二低频时钟信号在节点处或在输出端提供偏置电压。第三下拉电路可以基于反馈电压在节点处或输出端提供偏置电压。

3. 发明授权

US08340240B2 Shift register of LCD devices 有权
标题翻译： LCD设备的移位寄存器
公开(公告)号：US08340240B2
公开(公告)日：2012-12-25
申请号：US13492916
申请日：2012-06-10
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Chun-Hsin Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Chun-Hsin Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0219 , G11C19/28
摘要： A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.
摘要翻译：移位寄存器包括串联耦合的多个移位寄存器单元。接收输入端的输入电压和输出端的输出电压的每个移位寄存器单元包括节点，上拉驱动电路，上拉电路和第一至第三下拉电路。上拉驱动电路可以将输入电压传输到节点，并且上拉电路可以基于高频时钟信号和输入信号提供输出电压。第一下拉电路可以基于第一低频时钟信号在节点处或在输出端提供偏置电压。第二下拉电路可以基于第二低频时钟信号在节点处或在输出端提供偏置电压。第三下拉电路可以基于反馈电压在节点处或输出端提供偏置电压。

4. 发明授权

US08229058B2 Shift register of LCD devices 有权
公开(公告)号：US08229058B2
公开(公告)日：2012-07-24
申请号：US12607042
申请日：2009-10-27
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Chun-Hsin Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Chun-Hsin Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0219 , G11C19/28
摘要： A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.

5. 发明授权

US08031827B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08031827B2
公开(公告)日：2011-10-04
申请号：US13041794
申请日：2011-03-07
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.
摘要翻译：移位寄存器包括多个级，{Sn}，n = 1,2。。。，N，N为正整数。在一个实施例中，每级Sn包括一个上拉电路，该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端，用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时，上拉控制电路响应地产生提供给输入节点Qn的信号，以接通上拉电路，电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路，以及被配置为接收一个电压的下拉控制电路第三时钟信号CK2和第四时钟信号XCK2，并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和阶段Sn + 1。

6. 发明申请

US20110007863A1 SHIFT REGISTER 有权
标题翻译：移位寄存器
公开(公告)号：US20110007863A1
公开(公告)日：2011-01-13
申请号：US12877748
申请日：2010-09-08
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.
摘要翻译：移位寄存器包括多个级，{Sn}，n = 1,2。。。，N，N为正整数。在一个实施例中，每级Sn包括一个上拉电路，该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端，用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时，上拉控制电路响应地产生提供给输入节点Qn的信号，以接通上拉电路，电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路，以及被配置为接收一个电压的下拉控制电路第三时钟信号CK2和第四时钟信号XCK2，并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和阶段Sn + 1。

7. 发明授权

US07817771B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US07817771B2
公开(公告)日：2010-10-19
申请号：US12334874
申请日：2008-12-15
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.
摘要翻译：移位寄存器包括多个级，{Sn}，n = 1,2。。。，N，N为正整数。在一个实施例中，每级Sn包括一个上拉电路，该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端，用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时，上拉控制电路响应地产生提供给输入节点Qn的信号，以接通上拉电路，电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路，以及被配置为接收一个电压的下拉控制电路第三时钟信号CK2和第四时钟信号XCK2，并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和阶段Sn + 1。

8. 发明申请

US20110158376A1 SHIFT REGISTER 有权
公开(公告)号：US20110158376A1
公开(公告)日：2011-06-30
申请号：US13041794
申请日：2011-03-07
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/34
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.

9. 发明授权

US07924967B2 Shift register 有权
公开(公告)号：US07924967B2
公开(公告)日：2011-04-12
申请号：US12877748
申请日：2010-09-08
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.

10. 发明授权

US08422620B2 Shift registers 有权
标题翻译：移位寄存器
公开(公告)号：US08422620B2
公开(公告)日：2013-04-16
申请号：US12607156
申请日：2009-10-28
申请人： Kuo-Chang Su , Tsung-Ting Tsai , Yung-Chih Chen , Chun-Hsin Liu
发明人： Kuo-Chang Su , Tsung-Ting Tsai , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register is provided and includes a first shift registering unit and a second shift registering unit. The first shift registering unit generates a first trigger signal at a first output terminal and includes a first pull-down circuit. The second shift registering unit receives the first trigger signal and generates a second trigger signal at a second output terminal. The first trigger signal and the second trigger signal are sequentially asserted. The second shift registering unit includes a second pull-down circuit. The first pull-down circuit and the second pull-down circuit perform pull-down operations at different times. When the first pull-down circuit does not perform the pull-down operation, the second pull-down circuit performs pull-down operations to the first output terminal.
摘要翻译：提供一个移位寄存器，包括一个第一移位寄存单元和一个第二移位寄存单元。第一移位寄存单元在第一输出端产生第一触发信号，并包括第一下拉电路。第二移位寄存单元接收第一触发信号并在第二输出端产生第二触发信号。第一触发信号和第二触发信号被依次断言。第二移位登记单元包括第二下拉电路。第一下拉电路和第二下拉电路在不同时间执行下拉操作。当第一下拉电路不执行下拉操作时，第二下拉电路对第一输出端子执行下拉操作。

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