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1. 发明申请

US20110272739A1 METHOD FOR FABRICATING A STRAINED STRUCTURE 有权
标题翻译：制造应变结构的方法
公开(公告)号：US20110272739A1
公开(公告)日：2011-11-10
申请号：US12775006
申请日：2010-05-06
申请人： Tsung-Lin LEE , Chih-Hao CHANG , Chih-Hsin KO , Feng YUAN , Jeff J. XU
发明人： Tsung-Lin LEE , Chih-Hao CHANG , Chih-Hsin KO , Feng YUAN , Jeff J. XU
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L21/30604 , H01L21/31 , H01L21/31116 , H01L21/76 , H01L29/0653 , H01L29/0847 , H01L29/0856 , H01L29/0873 , H01L29/1608 , H01L29/165 , H01L29/6653 , H01L29/66553 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.
摘要翻译：一种用于衬底上的场效应晶体管的结构，其包括栅极堆叠，隔离结构以及位于栅叠层和隔离结构之间的衬底顶表面下方的源极/漏极（S / D）凹槽。该凹腔具有下部和上部。下部具有第一应变层和第一介电膜。第一应变层设置在隔离结构和第一介电膜之间。第一电介质膜的厚度小于第一应变层的厚度。上部具有覆盖在第一应变层和第一介电膜上的第二应变层。

2. 发明申请

US20080142888A1 ISOLATION SPACER FOR THIN SOI DEVICES 有权
标题翻译：用于薄SOI器件的隔离间隔器
公开(公告)号：US20080142888A1
公开(公告)日：2008-06-19
申请号：US12040877
申请日：2008-03-01
申请人： Chih-Hsin KO , Wen-Chin Lee , Yee-Chia Yeo , Chung-Hu Ke
发明人： Chih-Hsin KO , Wen-Chin Lee , Yee-Chia Yeo , Chung-Hu Ke
IPC分类号： H01L27/00
CPC分类号： H01L29/66772 , H01L27/1203 , H01L29/78618 , Y10S257/90
摘要： A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.
摘要翻译：半导体器件包括覆盖介电层的半导体台面，形成在半导体台面上的栅叠层，以及形成在半导体台面周围的隔离间隔物，并填充半导体台面的边缘处的任何底切区域。

3. 发明申请

US20080145982A1 ISOLATION SPACER FOR THIN SOI DEVICES 有权
公开(公告)号：US20080145982A1
公开(公告)日：2008-06-19
申请号：US12036616
申请日：2008-02-25
申请人： Chih-Hsin KO , Wen-Chin Lee , Yee-Chia Yeo , Chung-Hu Ke
发明人： Chih-Hsin KO , Wen-Chin Lee , Yee-Chia Yeo , Chung-Hu Ke
IPC分类号： H01L21/00 , H01L21/3205
CPC分类号： H01L29/66772 , H01L27/1203 , H01L29/78618 , Y10S257/90
摘要： A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.

4. 发明申请

US20130248927A1 CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的接触结构
公开(公告)号：US20130248927A1
公开(公告)日：2013-09-26
申请号：US13428972
申请日：2012-03-23
申请人： Cheng-Hsien WU , Chih-Hsin KO , Clement Hsingjen WANN
发明人： Cheng-Hsien WU , Chih-Hsin KO , Clement Hsingjen WANN
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L21/02609 , H01L21/28506 , H01L29/165 , H01L29/41791 , H01L29/4966 , H01L29/517 , H01L29/66636 , H01L29/78 , H01L29/7848 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： A contact structure for a semiconductor device includes a substrate comprising a major surface and a cavity. A bottom surface of the cavity is lower than the major surface. The contact structure also includes a strained material in the cavity, and a lattice constant of the strained material is different from lattice constant of the substrate. The contact structure also includes a first metal layer over the strained material, a dielectric layer over the first metal layer, and a second metal layer over the dielectric layer. The dielectric layer has a thickness ranging from 1 nm to 10 nm.
摘要翻译：用于半导体器件的接触结构包括包括主表面和腔的衬底。空腔的底面低于主表面。接触结构还包括空腔中的应变材料，并且应变材料的晶格常数不同于衬底的晶格常数。接触结构还包括应变材料上的第一金属层，第一金属层上的电介质层和介电层上的第二金属层。电介质层的厚度范围为1nm至10nm。

5. 发明申请

US20110117724A1 ISOLATION STRUCTURE FOR STRAINED CHANNEL TRANSISTORS 有权
标题翻译：应变通道晶体管的隔离结构
公开(公告)号：US20110117724A1
公开(公告)日：2011-05-19
申请号：US13013296
申请日：2011-01-25
申请人： Chih-Hsin KO , Yee-Chia YEO , Wen-Chin LEE , Chung-Hu GE
发明人： Chih-Hsin KO , Yee-Chia YEO , Wen-Chin LEE , Chung-Hu GE
IPC分类号： H01L21/762 , H01L21/763
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L29/1054 , H01L29/7846 , H01L29/7848
摘要： A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.
摘要翻译：公开了一种用于形成用于应变通道晶体管的改进的隔离结构的方法和系统。在一个示例中，形成包括填充有含氮衬里和间隙填料的沟槽的隔离结构。含氮衬垫使隔离结构能够减小对通道区域的压应变贡献。

6. 发明申请

US20130119370A1 STRAINED STRUCTURES OF SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件的应变结构
公开(公告)号：US20130119370A1
公开(公告)日：2013-05-16
申请号：US13296723
申请日：2011-11-15
申请人： Cheng-Hsien WU , Chih-Hsin KO , Clement Hsingjen WANN
发明人： Cheng-Hsien WU , Chih-Hsin KO , Clement Hsingjen WANN
IPC分类号： H01L29/772
CPC分类号： H01L29/7848 , H01L21/3065 , H01L29/0653 , H01L29/0847 , H01L29/20 , H01L29/22 , H01L29/267 , H01L29/66628 , H01L29/66636 , H01L29/66795
摘要： A strained structure of a semiconductor device is disclosed. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a gate stack on the major surface of the substrate; a shallow trench isolation (STI) disposed on one side of the gate stack, wherein the STI is within the substrate; and a cavity filled with a strained structure distributed between the gate stack and the STI, wherein the cavity comprises one sidewall formed by the STI, one sidewall formed by the substrate, and a bottom surface formed by the substrate, wherein the strained structure comprises a SiGe layer and a first strained film adjoining the sidewall of the STI.
摘要翻译：公开了半导体器件的应变结构。半导体器件的示例性结构包括：包括主表面的衬底; 在基板的主表面上的栅极堆叠; 设置在所述栅极堆叠的一侧上的浅沟槽隔离（STI），其中所述STI位于所述衬底内; 以及填充有分布在所述栅叠层和所述STI之间的应变结构的空腔，其中所述空腔包括由所述STI形成的一个侧壁，由所述基板形成的一个侧壁和由所述基板形成的底表面，其中所述应变结构包括 SiGe层和邻接STI侧壁的第一应变膜。

7. 发明申请

US20120211803A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD WITH IMPROVED EPITAXIAL QUALITY OF III-V COMPOUND ON SILICON SURFACES 有权
标题翻译：具有提高硅表面III-V化合物的外延质量的半导体器件和制造方法
公开(公告)号：US20120211803A1
公开(公告)日：2012-08-23
申请号：US13461595
申请日：2012-05-01
申请人： Cheng-Hsien WU , Chih-Hsin KO , Clement Hsingjen WANN
发明人： Cheng-Hsien WU , Chih-Hsin KO , Clement Hsingjen WANN
IPC分类号： H01L29/267
CPC分类号： H01L21/8258 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02538 , H01L21/02639 , H01L21/02667 , H01L21/02675
摘要： Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing.
摘要翻译：通过在沟槽中外延生长III-V族化合物半导体区域，然后对该区域进行封盖和退火来减少或消除堆叠故障。封盖层限制了原子从该区域的逃逸，并且能够与退火一起减少或消除堆垛层错。

8. 发明申请

US20120094467A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD WITH IMPROVED EPITAXIAL QUALITY OF III-V COMPOUND ON SILICON SURFACES 有权
公开(公告)号：US20120094467A1
公开(公告)日：2012-04-19
申请号：US13009151
申请日：2011-01-19
申请人： Cheng-Hsien WU , Chih-Hsin KO , Clement Hsingjen WANN
发明人： Cheng-Hsien WU , Chih-Hsin KO , Clement Hsingjen WANN
IPC分类号： H01L21/76
CPC分类号： H01L21/8258 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02538 , H01L21/02639 , H01L21/02667 , H01L21/02675
摘要： Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing.

9. 发明申请

US20110031538A1 CMOS STRUCTURE WITH MULTIPLE SPACERS 有权
标题翻译： CMOS结构与多个间隔
公开(公告)号：US20110031538A1
公开(公告)日：2011-02-10
申请号：US12757517
申请日：2010-04-09
申请人： Bor Chiuan HSIEH , Han-Ping CHUNG , Chih-Hsin KO , Bor-Wen CHAN , Hun-Jan TAO
发明人： Bor Chiuan HSIEH , Han-Ping CHUNG , Chih-Hsin KO , Bor-Wen CHAN , Hun-Jan TAO
IPC分类号： H01L29/78 , H01L29/49
CPC分类号： H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.
摘要翻译：半导体器件包括具有浅沟槽隔离和位于其中的源极/漏极区的衬底，位于源极/漏极区之间的衬底上的栅极堆叠，栅极堆叠的侧壁上的第一栅极间隔物和位于栅极堆叠的侧壁上的第二栅极间隔物第一栅极间隔物的侧壁。

10. 发明申请

US20110024794A1 FIN STRUCTURE FOR HIGH MOBILITY MULTIPLE-GATE TRANSISTOR 有权
标题翻译：用于高移动性多门控晶体管的FIN结构
公开(公告)号：US20110024794A1
公开(公告)日：2011-02-03
申请号：US12797839
申请日：2010-06-10
申请人： Chih-Hsin KO , Clement Hsingjen WANN
发明人： Chih-Hsin KO , Clement Hsingjen WANN
IPC分类号： H01L29/78 , H01L21/762 , H01L21/28
CPC分类号： H01L29/785 , H01L29/267 , H01L29/66795 , H01L29/7842
摘要： A vertical fin structure for a semiconductor transistor includes a semiconductor substrate, a fin layer on top of the substrate, a capping layer overlaying the fin layer, wherein the substrate comprises group IV semiconductor material, the fin layer comprises group IV semiconductor material, the capping layer comprises semiconductor compound from group III-V. The fin layer can comprise Ge, SiGe, SiC, or any combinations thereof. The semiconductor substrate can comprise Si, Ge, SiGe, or SiC. The capping layer can comprise GaAs, InGaAs, InAs, InSb, GaSb, GaN, InP, or any combinations thereof. The capping layer can provide more than a 4 percent lattice mismatch with the semiconductor substrate. The fin layer can be located in between shallow trench insulation (STI) layers that provide isolation from adjacent devices. The vertical fin structure can further include a high-k dielectric layer overlaying the capping layer and a metal gate layer overlaying the high-k dielectric layer.
摘要翻译：用于半导体晶体管的垂直翅片结构包括半导体衬底，衬底顶部的翅片层，覆盖翅片层的覆盖层，其中衬底包括IV族半导体材料，鳍层包括IV族半导体材料，封盖层包含III-V族的半导体化合物。鳍层可以包括Ge，SiGe，SiC或其任何组合。半导体衬底可以包括Si，Ge，SiGe或SiC。覆盖层可以包括GaAs，InGaAs，InAs，InSb，GaSb，GaN，InP或其任何组合。覆盖层可以提供与半导体衬底超过4％的晶格失配。翅片层可以位于提供与相邻装置隔离的浅沟槽绝缘（STI）层之间。垂直翅片结构还可以包括覆盖覆盖层的高k电介质层和覆盖高k电介质层的金属栅极层。

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