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1. 发明申请

US20160087817A1 DECISION FEEDBACK EQUALIZER SUMMATION CIRCUIT 审中-公开
标题翻译：决策反馈均衡器建立电路
公开(公告)号：US20160087817A1
公开(公告)日：2016-03-24
申请号：US14492237
申请日：2014-09-22
申请人： Ming-Chieh HUANG , Chan-Hong CHERN , Tao Wen CHUNG , Yuwen SWEI , Chih-Chang LIN , Tsung-Ching HUANG
发明人： Ming-Chieh HUANG , Chan-Hong CHERN , Tao Wen CHUNG , Yuwen SWEI , Chih-Chang LIN , Tsung-Ching HUANG
IPC分类号： H04L25/03 , H04L25/06 , H04L25/08
CPC分类号： H04L25/03057 , H04L25/06 , H04L25/08
摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.
摘要翻译：电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号由第一求和电路接收。第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号由第一求和电路接收。

2. 发明申请

US20140002332A1 PIXELS FOR DISPLAY 审中-公开
标题翻译：显示像素
公开(公告)号：US20140002332A1
公开(公告)日：2014-01-02
申请号：US13539181
申请日：2012-06-29
申请人： Tsung-Ching HUANG , Chan-Hong CHERN , Tao Wen CHUNG , Ming-Chieh HUANG , Chih-Chang LIN
发明人： Tsung-Ching HUANG , Chan-Hong CHERN , Tao Wen CHUNG , Ming-Chieh HUANG , Chih-Chang LIN
IPC分类号： G09G3/32
CPC分类号： G09G3/3233 , G09G3/3406 , G09G2300/0809 , G09G2300/0819 , G09G2300/0842 , G09G2320/0233 , G09G2320/0295 , G09G2320/045 , G09G2330/028
摘要： A current value of a first pixel and/or a current value of a second pixel of a display are adjusted until a value of a current difference is acceptable. The current value of the first pixel corresponds to a brightness level of the first pixel. The current value of the second pixel corresponds to a brightness level of the second pixel. Adjusting the current value of the first pixel involves adjusting a threshold voltage value of a transistor of the first pixel. Adjusting the current value of the second pixel involves adjusting a threshold voltage value of a transistor of the second pixel.
摘要翻译：调整显示器的第二像素的第一像素的当前值和/或当前值，直到电流差的值是可接受的。第一像素的当前值对应于第一像素的亮度级。第二像素的当前值对应于第二像素的亮度级。调整第一像素的当前值包括调整第一像素的晶体管的阈值电压值。调整第二像素的当前值包括调整第二像素的晶体管的阈值电压值。

3. 发明申请

US20130342247A1 CAPACTIVE LOAD PLL WITH CALIBRATION LOOP 有权
标题翻译：具有校准环路的电容负载PLL
公开(公告)号：US20130342247A1
公开(公告)日：2013-12-26
申请号：US13530136
申请日：2012-06-22
申请人： Chan-Hong CHERN , Tao Wen CHUNG , Ming-Chieh HUANG , Chih-Chang LIN , Tsung-Ching HUANG , Fu-Lung HSUEH
发明人： Chan-Hong CHERN , Tao Wen CHUNG , Ming-Chieh HUANG , Chih-Chang LIN , Tsung-Ching HUANG , Fu-Lung HSUEH
IPC分类号： H03L7/08
CPC分类号： H03L7/103 , H03L7/097 , H03L7/0995 , H03L7/1072 , H03L7/18 , H03L2207/06
摘要： A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
摘要翻译：电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

4. 发明申请

US20130335145A1 HIGH-SPEED TRANSIMPEDANCE AMPLIFIER 有权
标题翻译：高速放大放大器
公开(公告)号：US20130335145A1
公开(公告)日：2013-12-19
申请号：US13527365
申请日：2012-06-19
申请人： Tsung-Ching HUANG , Chan-Hong CHERN , Tao Wen CHUNG , Ming-Chieh HUANG , Chih-Chang LIN
发明人： Tsung-Ching HUANG , Chan-Hong CHERN , Tao Wen CHUNG , Ming-Chieh HUANG , Chih-Chang LIN
IPC分类号： H03F3/45
CPC分类号： H03F3/082 , H03F1/0205 , H03F3/08 , H03F3/3022 , H03F3/45179 , H03F3/45183 , H03F2200/216 , H03F2203/30031 , H03F2203/45222 , H03F2203/45644 , H03F2203/45686 , H03F2203/45702 , H03F2203/45724
摘要： A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to be coupled to an input signal. A second inverter has a second input node and a second output node. The second input node is configured to receive a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node.
摘要翻译：跨阻放大器包括具有第一输入节点和第一输出节点的第一反相器。第一输入节点被配置为耦合到输入信号。第二反相器具有第二输入节点和第二输出节点。第二输入节点被配置为接收参考电压端子。第一反相器和第二反相器被配置为在第一输出节点和第二输出节点之间提供差分输出电压信号。

5. 发明申请

US20140015582A1 SLICER AND METHOD OF OPERATING THE SAME 有权
标题翻译： SLICER及其操作方法
公开(公告)号：US20140015582A1
公开(公告)日：2014-01-16
申请号：US13547396
申请日：2012-07-12
申请人： Ming-Chieh HUANG , Chan-Hong CHERN , Tao Wen CHUNG , Chih-Chang LIN , Tsung-Ching HUANG , Derek C. TAO
发明人： Ming-Chieh HUANG , Chan-Hong CHERN , Tao Wen CHUNG , Chih-Chang LIN , Tsung-Ching HUANG , Derek C. TAO
IPC分类号： H03K3/356
CPC分类号： H03K5/08 , H03K3/356139 , H04L27/01
摘要： This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.
摘要翻译：该描述涉及包括第一锁存器的限幅器。第一锁存器包括被配置为接收第一时钟信号的评估晶体管和被配置为接收第二时钟信号的显影晶体管。第一时钟信号与第二时钟信号不同。第一锁存器包括被配置为接收第一和第二互补输入的第一和第二输入晶体管。第一锁存器包括配置成接收第三时钟信号的至少一个预充电晶体管。第一锁存器还包括至少一个交叉锁存晶体管对，该至少一个交叉锁存晶体管对连接在评估晶体管与第一和第二输出节点之间。切片器包括连接到第一和第二输出节点和第三输出节点的第二锁存器。切片器包括连接到第三输出节点并被配置为产生最终输出信号的缓冲器。

6. 发明申请

US20130346811A1 DECISION FEEDBACK EQUALIZER 有权
标题翻译：决策反馈均衡器
公开(公告)号：US20130346811A1
公开(公告)日：2013-12-26
申请号：US13528877
申请日：2012-06-21
申请人： Ming-Chieh HUANG , Chan-Hong CHERN , Tao Wen CHUNG , Yuwen SWEI , Chih-Chang LIN , Tsung-Ching HUANG
发明人： Ming-Chieh HUANG , Chan-Hong CHERN , Tao Wen CHUNG , Yuwen SWEI , Chih-Chang LIN , Tsung-Ching HUANG
IPC分类号： G06F1/04 , G06F11/00
CPC分类号： H04L25/03057 , H04L25/06 , H04L25/08
摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.
摘要翻译：电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号由第一求和电路接收。第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号由第一求和电路接收。

7. 发明申请

US20140037035A1 PHASE INTERPOLATOR FOR CLOCK DATA RECOVERY CIRCUIT WITH ACTIVE WAVE SHAPING INTEGRATORS 有权
标题翻译：用于具有主动波形整合器的时钟数据恢复电路的相位插值器
公开(公告)号：US20140037035A1
公开(公告)日：2014-02-06
申请号：US13564758
申请日：2012-08-02
申请人： Tao Wen CHUNG , Chan-Hong CHERN , Ming-Chieh HUANG , Chih-Chang LIN , Yuwen SWEI
发明人： Tao Wen CHUNG , Chan-Hong CHERN , Ming-Chieh HUANG , Chih-Chang LIN , Yuwen SWEI
IPC分类号： H03D3/24
CPC分类号： H03K5/135 , H03H11/20 , H03K2005/00052 , H04L7/0029
摘要： A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.
摘要翻译：用于CDR电路的相位插值器产生具有在两个输入时钟上的电平转换之间的电平转换的输出时钟。输入时钟驱动交叉耦合差分放大器，输出可根据输入控制值通过可变电流节流或转向相位变化。差分放大器产生一个输出信号，该输出信号跨越在引导输入时钟之间的转换开始到延迟输入时钟转换结束之间的时间。输出时钟是线性的，只要两个输入时钟的转换重叠即可。每个具有串联电阻和电容反馈路径的放大器的积分器耦合到交叉耦合差分放大器的每个输入，这增强了输入时钟上升时间的重叠，并提高了内插输出信号的线性度。

8. 发明申请

US20140015611A1 METHOD AND APPARATUS FOR FEEDBACK-BASED RESISTANCE CALIBRATION 有权
标题翻译：基于反馈电阻校准的方法和装置
公开(公告)号：US20140015611A1
公开(公告)日：2014-01-16
申请号：US13547101
申请日：2012-07-12
申请人： Tao Wen CHUNG , Chan-Hong CHERN , Ming-Chieh HUANG , Chih-Chang LIN , Yuwen SWEI
发明人： Tao Wen CHUNG , Chan-Hong CHERN , Ming-Chieh HUANG , Chih-Chang LIN , Yuwen SWEI
IPC分类号： H03F3/04
CPC分类号： G01R31/2621
摘要： A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage.
摘要翻译：电路具有包括第一电阻器和与第一电阻器并联耦合的第一和第二晶体管的第一电路模块。第一电阻器和第一和第二晶体管在第一节点耦合在一起。当第一节点的电压从第一电压增加到第二电压时，跨第一电路模块的等效电阻增加，并且第一电路模块上的等效电阻随着第一节点的电压从第二电压增加而减小到第三电压。

9. 发明申请

US20130099767A1 DRIVERS HAVING T-COIL STRUCTURES 有权
标题翻译：具有T型线圈结构的驱动器
公开(公告)号：US20130099767A1
公开(公告)日：2013-04-25
申请号：US13278742
申请日：2011-10-21
申请人： Ming-Chieh HUANG , Tao Wen CHUNG , Chan-Hong CHERN , Chih-Chang LIN , Yuwen SWEI , Chiang PU
发明人： Ming-Chieh HUANG , Tao Wen CHUNG , Chan-Hong CHERN , Chih-Chang LIN , Yuwen SWEI , Chiang PU
IPC分类号： G05F3/02
CPC分类号： H03H11/44 , H01S5/0427 , H04B10/504
摘要： A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage.
摘要翻译：驱动器包括具有至少一个输入节点和至少一个第一输出节点的第一驱动器级。第一驱动级包括邻近于至少一个第一输出节点设置的T型线圈结构。 T型线圈结构包括第一组电感器，每个电感器可操作以提供第一电感。第二组电感器以并行方式与第一组电感器电耦合。第二组电感器可操作以提供第二电感。第二驱动级与第一驱动器级电耦合。

10. 发明申请

US20120262212A1 MULTIPLE-PHASE CLOCK GENERATOR 有权
标题翻译：多相时钟发生器
公开(公告)号：US20120262212A1
公开(公告)日：2012-10-18
申请号：US13084817
申请日：2011-04-12
申请人： Chih-Chang LIN , Chan-Hong CHERN , Ming-Chieh HUANG , Tao Wen CHUNG
发明人： Chih-Chang LIN , Chan-Hong CHERN , Ming-Chieh HUANG , Tao Wen CHUNG
IPC分类号： H03K5/15
CPC分类号： H03K5/15013
摘要： A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2N dividers, where N is a positive integer number. Each divider in the first stage is configured to divide a first clock frequency of the first stage clock input by 2 to provide a first stage output. Each divider in the N-th stage is configured to divide an N-th clock frequency of an N-th stage clock input by 2 to provide an N-th stage output. The N-th stage outputs from the dividers in the N-th stage provide 2N-phase clock signals that are equally distributed with a same phase difference between adjacent phase clock signals.
摘要翻译：多相时钟发生器包括至少一个分频器级。时钟信号作为第一级时钟输入提供给分频器的第一级中的分频器。第N级包括2N个分频器，其中N是正整数。第一级中的每个分频器被配置为将第一级时钟输入的第一时钟频率除以2以提供第一级输出。第N级中的每个除法器被配置为将输入的第N级时钟的第N个时钟频率除以2以提供第N级输出。在第N级的分频器的第N级输出提供2N相位时钟信号，它们在相邻的相位时钟信号之间以相同的相位差均匀分布。

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