会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Information processing system consisting of an arithmetic control unit
formed into a one-chip typed by application of a highly-integrated
semiconductor device
    • 信息处理系统由通过应用高度集成的半导体器件形成为单片的算术控制单元构成
    • US4616331A
    • 1986-10-07
    • US236116
    • 1981-02-19
    • Tsuneo KinoshitaFumitaka SatoIsamu Yamazaki
    • Tsuneo KinoshitaFumitaka SatoIsamu Yamazaki
    • G06F9/38G06F9/30G06F13/00
    • G06F9/3812G06F9/3802G06F9/3804
    • In a one-chip high density arithmetic control unit capable of prefetching user's instructions from main memory, an arithmetic logic unit (ALU) subtracts the contents of a location counter holding the address of the next instruction to be executed, from the contents of a memory address register holding an address into which data will be written. The difference is fed through the gates connected to the ALU for determining whether or not prefetched instructions will have to be refetched. An address matching mechanism provided outside the one-chip arithmetic control unit includes a comparator for comparing memory addresses to a preset execution stop address. The output signal of the comparator is stored in a memory section which is provided to correspond to the prefetched instruction buffer, and when an instruction stored in the prefetched instruction buffer is transferred to an instruction register, the signal stored in the corresponding memory section is also read out and used to determine whether to stop execution. Further, whenever access is made to main memory a signal indicating whether the access is legal is externally generated and may be stored in a second memory section. Like the address matching signal, this signal is read out when the corresponding instruction from the prefetched instruction buffer is transferred to the instruction register. An illegal address interruption is produced when this signal indicates that the address was illegal.
    • 在能够从主存储器预取用户指令的单芯片高密度算术控制单元中,算术逻辑单元(ALU)从存储器的内容中减去保持要执行的下一个指令的地址的位置计数器的内容 地址寄存器保存写入数据的地址。 差异通过连接到ALU的门馈送,以确定是否必须重新获取预取指令。 在单芯片运算控制单元外提供的地址匹配机构包括比较器,用于将存储器地址与预设的执行停止地址进行比较。 比较器的输出信号存储在与预取指令缓冲器相对应的存储器部分中,并且当存储在预取指令缓冲器中的指令被传送到指令寄存器时,存储在相应存储器部分中的信号也是 读出并用于确定是否停止执行。 此外,每当访问主存储器时,指示是否合法的信号是外部生成的,并且可以存储在第二存储器部分中。 类似地址匹配信号,当来自预取指令缓冲器的相应指令被传送到指令寄存器时,该信号被读出。 当该信号表示该地址是非法的时,产生非法地址中断。
    • 3. 发明授权
    • Information processing system including a one-chip arithmetic control
unit
    • 信息处理系统,包括单片机运算控制单元
    • US4466055A
    • 1984-08-14
    • US244623
    • 1981-03-17
    • Tsuneo KinoshitaFumitaka SatoIsamu Yamazaki
    • Tsuneo KinoshitaFumitaka SatoIsamu Yamazaki
    • G06F13/40G06F13/42G06F15/78G06F3/00G06F13/00
    • G06F13/4018G06F13/4217G06F15/7832
    • In an information processing system in which an arithmetic control unit is formed on one chip by very large scale integration and is connected to external devices by a common bus, microinstructions from an externally-connected control memory, memory information output from an external main memory and information output from I/O devices, can be received by the arithmetic control unit on the common bus. An external setting signal for selecting whether the instruction system of the arithmetic control unit is to be enabled or disabled is input to the arithmetic control unit on the common bus simultaneously with the fetching of a microinstruction. A bus width setting signal from an I/O device is also input to the arithmetic control unit on the common bus simultaneously with the fetching of a microinstruction, and the CPU determines whether the data width of an I/O device is 8 bits or 16 bits. An interruption signal from an I/O device and a signal indicating an abnormal condition of a power source, for example, may be input to the arithmetic control unit from external devices on the common bus as part of a group of external signals occupying only a portion of the common bus simultaneously with the fetching of a microinstruction on the remaining portion of the common bus. When exchanging a plurality of kinds of data with different phases between the arithmetic control unit and external devices on the common bus, an external status signal unique to each phase is input to the arithmetic control unit on a common signal line in synchronism with each phase.
    • 在一种信息处理系统中,其中通过非常大规模的集成在一个芯片上形成运算控制单元,并且通过公共总线连接到外部设备,来自外部连接的控制存储器的微指令,从外部主存储器输出的存储器信息和 I / O设备输出的信息可由公共总线上的运算控制单元接收。 用于选择运算控制单元的指令系统是否被使能或禁用的外部设置信号在获取微指令时同时在公共总线上输入到运算控制单元。 来自I / O设备的总线宽度设置信号也被同时输入到公共总线上的算术控制单元,同时获取微指令,并且CPU确定I / O设备的数据宽度是8位还是16 位。 来自I / O设备的中断信号和指示电源异常状态的信号例如可以从公共总线上的外部设备输入到算术控制单元,作为仅占用一个 公共总线的一部分同时在公共总线的剩余部分上取出微指令。 当在公共总线上的算术控制单元和外部设备之间交换具有不同相位的多种数据时,每个相位独有的外部状态信号与每个相位同步地在公共信号线上输入到运算控制单元。