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1. 发明授权

US06473865B1 Apparatus comprising clock control circuit, method of controlling clock signal and device using internal clock signal synchronized to external clock signal 有权
标题翻译：装置包括时钟控制电路，控制时钟信号的方法和使用与外部时钟信号同步的内部时钟信号的装置
公开(公告)号：US06473865B1
公开(公告)日：2002-10-29
申请号：US09272171
申请日：1999-03-18
申请人： Masahiro Kamoshida , Haruki Toda , Tsuneaki Fuse , Yukihito Oowaki
发明人： Masahiro Kamoshida , Haruki Toda , Tsuneaki Fuse , Yukihito Oowaki
IPC分类号： G06F112
CPC分类号： G06F1/3287 , G06F1/10 , G06F1/3203 , Y02D10/126 , Y02D10/171
摘要： Each delay unit is divided into two delay unit groups, the preceding stage side and the succeeding stage side. To the delay unit group in the preceding stage side, power supply voltage is supplied via a power supply terminal, and to each delay unit of the delay unit group in the succeeding stage side, power supply voltage is supplied from the power supply terminal via a power supply control switch. A forward-pulse detecting circuit detects that forward pulse was propagated to a stage between the N-th stage and a stage a predetermined number of stages before the N-th, and outputs the detected result to the power supply control switch. With this operation, when forward pulse is propagated to the (N+1)th stage, power supply voltage is supplied also to the delay unit group in the succeeding stage side. As electric power is not supplied to the delay unit group in the succeeding stage side when forward pulse is not propagated to the (N+1)th stage, wasteful consumption of electric power is prevented.
摘要翻译：每个延迟单元被分成两个延迟单元组，即前级侧和后级侧。对于前级侧的延迟单元组，经由电源端子向后级侧的延迟单元组的延迟单元供给电源电压，经由电源端子从电源端子供给电源电压电源控制开关。正向脉冲检测电路检测正向脉冲传播到第N级的第N级与预定级的级之间的级，并将检测结果输出到电源控制开关。通过这种操作，当正向脉冲传播到第（N + 1）级时，电源电压也被提供给后级侧的延迟单元组。当正向脉冲不传播到第（N + 1）级时，由于不向后级侧的延迟单元组提供电力，所以防止了浪费的电力消耗。

2. 发明授权

US06393080B1 Apparatus comprising clock control circuit and device using internal clock signal synchronized to external clock signal 有权
标题翻译：装置包括时钟控制电路和使用与外部时钟信号同步的内部时钟信号的装置
公开(公告)号：US06393080B1
公开(公告)日：2002-05-21
申请号：US09271329
申请日：1999-03-18
申请人： Masahiro Kamoshida , Haruki Toda , Tsuneaki Fuse , Yukihito Oowaki
发明人： Masahiro Kamoshida , Haruki Toda , Tsuneaki Fuse , Yukihito Oowaki
IPC分类号： H04L700
CPC分类号： G11C7/222 , G11C7/22 , H03K5/135 , H03L7/00 , H04L7/0337
摘要： A state-holding circuit initializing circuit initializes state-holding circuit when propagation of forward pulse to the forward-pulse delay circuits in the last stage is detected. With this operation, synchronization is established in a short time from the resumption of outputting from a receiver. The state-holding circuit control circuit also controls the reset timing of the state-holding circuit. A forward-pulse adjusting circuit controls the pulse width of forward pulse to be supplied to the forward-pulse delay line. With this operation, the stages from the stage where rearward pulse was generated to the first stage are securely turned to the set state, enabling propagation of rearward pulse and synchronization is established. Thus, synchronization is established reliably even when output from a receiver stops or the duty of an external clock signal is heavy.
摘要翻译：状态保持电路初始化电路在正向脉冲传播到最后一级的正向脉冲延迟电路时，初始化状态保持电路。通过该操作，从恢复从接收器输出的短时间内建立同步。状态保持电路控制电路还控制状态保持电路的复位定时。正向脉冲调整电路控制要提供给正向脉冲延迟线的正向脉冲的脉冲宽度。通过该动作，从产生向后脉冲的阶段到第一阶段的阶段被牢固地转到设定状态，从而能够建立向后脉冲的传播和同步。因此，即使从接收器的输出停止或外部时钟信号的占空比很重，也能够可靠地建立同步。

3. 发明授权

US6084453A Clock converting circuit 失效
标题翻译：时钟转换电路
公开(公告)号：US6084453A
公开(公告)日：2000-07-04
申请号：US105959
申请日：1998-06-29
申请人： Tsuneaki Fuse , Masahiro Kamoshida , Haruki Toda , Yukihito Oowaki
发明人： Tsuneaki Fuse , Masahiro Kamoshida , Haruki Toda , Yukihito Oowaki
IPC分类号： H03K5/04 , G06F1/06 , G11C11/407 , G11C11/4076 , H03K5/13 , H03K5/156 , H03K7/08
CPC分类号： H03K5/1565 , H03K5/133
摘要： A cycle measuring circuit 3 measures a cycle of an external clock signal, which is approximately m times a unit time. A number converting circuit 5 and a time converting circuit 7 cooperate, generating a pulse signal delayed by m/2.sup.K times the unit time, or by 1/2.sup.K times the cycle of the external clock signal. A logic circuit 8 generates an internal clock signal which rises in synchronism with the external clock signal and falls in synchronism with the pulse signal thus delayed. Hence, the internal clock signal has the same cycle as the external clock signal and has a desired duty ratio of (1/2.sup.K).times.100%.
摘要翻译：周期测量电路3测量大约是单位时间的m倍的外部时钟信号的周期。数字转换电路5和时间转换电路7协调，产生延迟了单位时间的m / 2K倍的脉冲信号，或者是外部时钟信号的周期的1 / 2K倍。逻辑电路8产生与外部时钟信号同步上升的内部时钟信号，并且与延迟的脉冲信号同步地下降。因此，内部时钟信号具有与外部时钟信号相同的周期，并且具有（1 / 2K）×100％的期望占空比。

4. 发明授权

US06388484B1 Clock control circuit 有权
标题翻译：时钟控制电路
公开(公告)号：US06388484B1
公开(公告)日：2002-05-14
申请号：US09243483
申请日：1999-02-03
申请人： Masahiro Kamoshida , Haruki Toda , Tsuneaki Fuse , Yukihito Oowaki
发明人： Masahiro Kamoshida , Haruki Toda , Tsuneaki Fuse , Yukihito Oowaki
IPC分类号： H03L700
CPC分类号： H03K5/135 , H03L7/00
摘要： In this clock control circuit, clock signal CLK from a receiver is supplied to a pulse generating circuit, and the pulse generating circuit generates forward pulse, which is clock signal CLK delayed as much time as A, and pulse s which is synchronized with dock signal CLK and has a pulse width of A. Consequently, as forward pulse becomes “H” while pulse s is “L” without generating pulse which width is narrower than A, the edge part of forward pulse is securely propagated by a forward-pulse delay line even if it is high frequency. Propagation of forward pulse stops at rising edge of pulse s, and rearward pulse is generated in a corresponding stage. This rearward pulse is propagated by a rearward-pulse delay line, and outputted from an output buffer. As each delay element of forward-pulse delay line and rearward-pulse delay line is configured with one-gate circuits, propagation time of forward pulse and rearward pulse can be adjusted to the time (&tgr;−A) with high accuracy to improve synchronization accuracy.
摘要翻译：在该时钟控制电路中，来自接收机的时钟信号CLK被提供给脉冲发生电路，并且脉冲发生电路产生正向脉冲，其是时钟信号CLK延迟多达A个时间，脉冲s与停靠信号同步 CLK并具有A的脉冲宽度。因此，当脉冲s为“L”时，正向脉冲变为“H”，而不产生宽度比A窄的脉冲，正向脉冲的边沿部分通过正向脉冲延迟可靠地传播即使是高频也行。正向脉冲的传播在脉冲s的上升沿停止，在相应的阶段产生向后的脉冲。该后向脉冲由后向脉冲延迟线传播，并从输出缓冲器输出。由于正向脉冲延迟线和后向脉冲延迟线的每个延迟元件都配置有单门电路，可以高精度地将正向脉冲和向后脉冲的传播时间调整到时间（＆Tgr--A），以提高同步性准确性。

5. 发明授权

US6087893A Semiconductor integrated circuit having suppressed leakage currents 失效
标题翻译：具有抑制泄漏电流的半导体集成电路
公开(公告)号：US6087893A
公开(公告)日：2000-07-11
申请号：US956956
申请日：1997-10-23
申请人： Yukihito Oowaki , Tsuneaki Fuse
发明人： Yukihito Oowaki , Tsuneaki Fuse
IPC分类号： H01L27/092 , G05F1/46 , G05F3/02 , H01L21/8238 , H01L29/786 , H03K17/687 , H03K19/0175 , H03K19/0948
CPC分类号： G05F1/46
摘要： A stable high-speed integrated circuit driven by a wide range of low voltages and consuming low power. A MOSFET is used wherein signals are applied to its gate and body for forming a circuit block which comprises a transistor network and at least one buffer circuit. Each buffer circuit has at least two configurations. A plurality of circuit blocks are formed on the same IC chip. Any of the configurations of the buffer circuit may be selected according to the magnitude of the capacitance of the load driven by the circuit block.
摘要翻译：稳定的高速集成电路，由各种低电压驱动并消耗低功耗。使用MOSFET，其中向其栅极和主体施加信号以形成包括晶体管网络和至少一个缓冲电路的电路块。每个缓冲电路具有至少两种配置。在同一IC芯片上形成多个电路块。可以根据由电路块驱动的负载的电容的大小来选择缓冲电路的任何配置。

6. 发明授权

US5867040A Integrated circuit with stacked sub-circuits between Vcc and ground so as to conserve power and reduce the voltage across any one transistor 失效
标题翻译：集成电路，具有Vcc和地之间的堆叠子电路，以节省功率并降低任何一个晶体管的电压
公开(公告)号：US5867040A
公开(公告)日：1999-02-02
申请号：US593275
申请日：1996-01-29
申请人： Tsuneaki Fuse , Yukihito Oowaki
发明人： Tsuneaki Fuse , Yukihito Oowaki
IPC分类号： G11C11/407 , G11C5/14 , H01L21/822 , H01L27/04 , H03K19/00 , H01L25/00
CPC分类号： G11C5/147 , H03K19/0016 , Y10T307/352
摘要： The semiconductor integrated circuit device of the present invention includes a plurality of integrated circuits. The scheduling circuit selects an arbitrary number of integrated circuit from the plurality of integrated circuits, and connects the selected integrated circuits between the power line and the ground line such that the selected integrated circuits are arranged in series or in series-parallel. The scheduling circuit sets a combination of connection of the selected integrated circuits such that the consumption power of the total of the selected integrated circuits becomes minimum. The voltage control circuit sets a potential of a serial connecting portion of the selected integrated circuits. The data control circuit has an input output circuit for inputting and outputting data between the selected integrated circuits, and the outside, and a level conversion circuit for converting a level of data between certain integrated circuits.
摘要翻译：本发明的半导体集成电路器件包括多个集成电路。调度电路从多个集成电路中选择任意数量的集成电路，并且将所选择的集成电路在电力线和接地线之间连接，使得所选择的集成电路串联或并联布置。调度电路设置所选择的集成电路的连接的组合，使得所选择的集成电路的总体的消耗功率变得最小。电压控制电路设定所选择的集成电路的串联连接部分的电位。数据控制电路具有用于在所选择的集成电路之间输入和输出数据的输入输出电路和外部，以及用于转换某些集成电路之间的数据电平的电平转换电路。

7. 发明授权

US06177811B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06177811B1
公开(公告)日：2001-01-23
申请号：US09348623
申请日：1999-07-06
申请人： Tsuneaki Fuse , Yukihito Oowaki , Yoko Shuto
发明人： Tsuneaki Fuse , Yukihito Oowaki , Yoko Shuto
IPC分类号： H03K190944
CPC分类号： H03K19/215 , H01L27/1203 , H03K19/09441 , H03K19/0948
摘要： A semiconductor integrated circuit device includes a semiconductor substrate, a MOS transistor formed on the semiconductor substrate and having a first gate, wherein a first signal supplied to the first gate and a second signal supplied to a substrate region corresponding to the semiconductor substrate are combined with each other so that one logical signal is transmitted.
摘要翻译：半导体集成电路器件包括半导体衬底，形成在半导体衬底上并具有第一栅极的MOS晶体管，其中提供给第一栅极的第一信号和提供给对应于半导体衬底的衬底区域的第二信号与使得一个逻辑信号被发送。

8. 发明授权

US06392467B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06392467B1
公开(公告)日：2002-05-21
申请号：US09612679
申请日：2000-07-10
申请人： Yukihito Oowaki , Tsuneaki Fuse
发明人： Yukihito Oowaki , Tsuneaki Fuse
IPC分类号： H03K17687
CPC分类号： G05F1/46
摘要： A stable high-speed integrated circuit driven by a wide range of low voltages and consuming low power. A MOSFET is used wherein signals are applied to its gate and body for forming a circuit block which comprises a transistor network and at least one buffer circuit. Each buffer circuit has at least two configurations. A plurality of circuit blocks are formed on the same IC chip. Any of the configurations of the buffer circuit may be selected according to the magnitude of the capacitance of the load driven by the circuit block.
摘要翻译：稳定的高速集成电路，由各种低电压驱动并消耗低功耗。使用MOSFET，其中向其栅极和主体施加信号以形成包括晶体管网络和至少一个缓冲电路的电路块。每个缓冲电路具有至少两种配置。在同一IC芯片上形成多个电路块。可以根据由电路块驱动的负载的电容的大小来选择缓冲电路的任何配置。

9. 发明授权

US06295241B1 Dynamic random access memory device 失效
标题翻译：动态随机存取存储器
公开(公告)号：US06295241B1
公开(公告)日：2001-09-25
申请号：US08251649
申请日：1994-05-31
申请人： Shigeyoshi Watanabe , Tsuneaki Fuse , Koji Sakui , Masako Ohta , Yukihito Oowaki , Kenji Numata , Fujio Masuoka
发明人： Shigeyoshi Watanabe , Tsuneaki Fuse , Koji Sakui , Masako Ohta , Yukihito Oowaki , Kenji Numata , Fujio Masuoka
IPC分类号： G11C702
CPC分类号： G11C11/4091 , G11C7/062 , G11C7/14 , G11C11/4099
摘要： Here is disclosed a dynamic semiconductor memory of high integration density, which has parallel word lines and parallel bit lines formed on a substrate. The bit lines include a pair of bit lines. A memory cell is coupled to a word line and to one bit line of the bit-line pair. The memory cell is composed of MOSFETs of a submicron size. A sense amplifier section is connected to the pair of bit lines, and senses and amplifies the potential difference between the pair of bit lines in a data readout mode. The amplifier section has a BIMOS structure, having MOSFETs and bipolar transistors. It has a driver section comprised of bipolar transistors.
摘要翻译：这里公开了具有高集成度密度的动态半导体存储器，其具有在基板上形成的并行字线和并行位线。位线包括一对位线。存储器单元耦合到字线和位线对的一个位线。存储单元由亚微米尺寸的MOSFET组成。读出放大器部分连接到一对位线，并且在数据读出模式下感测和放大一对位线之间的电位差。放大器部分具有BIMOS结构，具有MOSFET和双极晶体管。它具有由双极晶体管组成的驱动器部分。

10. 发明授权

US08067963B2 Sense-amplifier control circuit and controlling method of sense amplifier 有权
标题翻译：感应放大器控制电路及读出放大器的控制方法
公开(公告)号：US08067963B2
公开(公告)日：2011-11-29
申请号：US12565478
申请日：2009-09-23
申请人： Seiro Imai , Tsuneaki Fuse
发明人： Seiro Imai , Tsuneaki Fuse
IPC分类号： G01R19/00
CPC分类号： H03F3/45179
摘要： A sense amplifier control circuit includes an initial-voltage setting circuit configured to set a control signal to an initial voltage, the control signal controlling a sensing operation of a sense amplifier, and a control-signal-level adjusting circuit configured to first change a voltage level of the control signal from the initial voltage to a voltage level at which the sense amplifier can execute a current sensing, and is configured to second change, after a predetermined time elapses, the voltage level at which the sense amplifier can execute the current sensing to a voltage level at which the sense amplifier can execute a voltage sensing.
摘要翻译：读出放大器控制电路包括初始电压设定电路，其被配置为将控制信号设定为初始电压，控制信号控制感测放大器的感测操作，以及控制信号电平调整电路，其被配置为首先改变电压控制信号的电平从初始电压到读出放大器可以执行电流检测的电压电平，并且被配置为在预定时间过去之后进行第二次改变，读出放大器可以执行电流感测的电压电平到感测放大器可以执行电压感测的电压电平。

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