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1. 发明授权

US4992977A Cache memory device constituting a memory device used in a computer 失效
标题翻译：构成计算机中使用的存储装置的高速缓存存储装置
公开(公告)号：US4992977A
公开(公告)日：1991-02-12
申请号：US173296
申请日：1988-03-25
申请人： Tsukasa Matoba , Takeshi Aikawa , Ken-ichi Maeda , Mitsuo Saito , Mitsuyoshi Okamura
发明人： Tsukasa Matoba , Takeshi Aikawa , Ken-ichi Maeda , Mitsuo Saito , Mitsuyoshi Okamura
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3812 , G06F12/0804 , G06F12/0848
摘要： A cache memory device comprises a data cache memory, an instruction cache memory, an instruction code area change detector, and an instruction code change processor. The instruction code area change detector decides whether writing access to the data cache memory by the processor is to a data area or to an instruction area of a main memory. The instruction code change processor passes the data cache memory to perform direct writing into the main memory when the writing access is to the instruction area, and, when data for a processor address is cached in a tag section of the instruction cache memory, invalidates the effective flag of the tag section.
摘要翻译：高速缓冲存储器装置包括数据高速缓存存储器，指令高速缓存存储器，指令代码区域改变检测器和指令代码改变处理器。指令代码区域改变检测器决定处理器对数据高速缓冲存储器的写入写入是到数据区还是主存储器的指令区。当写入访问指令区时，指令代码变更处理器通过数据高速缓冲存储器来执行直接写入主存储器，并且当处理器地址的数据被缓存在指令高速缓存存储器的标签部分中时，使标签部分的有效标志。

2. 发明授权

US5021993A Device for saving and restoring register information 失效
标题翻译：保存和恢复注册信息的设备
公开(公告)号：US5021993A
公开(公告)日：1991-06-04
申请号：US175224
申请日：1988-03-30
申请人： Tsukasa Matoba , Takeshi Aikawa , Mitsuyoshi Okamura , Ken-ichi Maeda , Mitsuo Saito
发明人： Tsukasa Matoba , Takeshi Aikawa , Mitsuyoshi Okamura , Ken-ichi Maeda , Mitsuo Saito
IPC分类号： G06F9/30 , G06F9/38 , G06F9/42 , G06F9/46 , G06F9/48 , G11C7/10
CPC分类号： G06F9/30189 , G06F9/30116 , G06F9/30123 , G06F9/4426 , G06F9/462 , G11C7/1006
摘要： Each register of an internal register unit of a microprocessor has a pair of register cells consisting of first and second cells having the same register address. When one of these cells is selected, the other cell non-selected serves as a "back-up cell" for the selected cell. Each register of the register unit has a flag bit for storing a selector flag representing which cell of the pair of cells of the register is currently selected, and a flag bit for storing a change flag representing whether register information of the register is rewritten after a selected cell is changed between the first and second cells of the register. When the register information is stored in one of the pair of cells currently being selected of a certain register and is to be rewritten with another new information, the other cell of the register is selected to store the new information therein. The original register information is held in the first cell, thereby eliminating necessity of saving the original register information to a main memory at this stage. When the original register information is required again, the original register information can be rapidly restored, by only selecting the first cell again, in the corresponding register without executing save/restore processing between the register unit and the main memory.

3. 发明授权

US4945510A Register device 失效
标题翻译：注册设备
公开(公告)号：US4945510A
公开(公告)日：1990-07-31
申请号：US133737
申请日：1987-12-16
申请人： Ken-ichi Maeda , Mitsuo Saito , Takeshi Aikawa , Tsukasa Matoba , Mitsuyoshi Okamura
发明人： Ken-ichi Maeda , Mitsuo Saito , Takeshi Aikawa , Tsukasa Matoba , Mitsuyoshi Okamura
IPC分类号： G06F9/34 , G06F9/42 , G06F9/46
CPC分类号： G06F9/30116 , G06F9/4426 , G06F9/462
摘要： A register device includes a register set group, a switching control unit, a write control unit, a write flag memory unit, and a read control unit. The register set group consists of a plurality of register sets each constituted by a plurality of registers. The switching control unit selects a register set to be used in processing from the register set group in response to a saving/recovery instruction. The write control unit writes data in registers of the register set selected by the switching control unit in response to a write instruction. A write flag representing whether data is written in each of the registers is held by the write flag memory unit. The read control unit determines, in response to a read instruction, a register in which data is written most recently of a plurality of registers corresponding to each other between the register sets with reference to the write flags, thereby reading out data from the register.

4. 发明授权

US5034885A Cache memory device with fast data-write capacity 失效
标题翻译：具有快速数据写入能力的缓存存储器件
公开(公告)号：US5034885A
公开(公告)日：1991-07-23
申请号：US321398
申请日：1989-03-10
申请人： Tsukasa Matoba , Takeshi Aikawa , Mitsuyoshi Okamura , Kenichi Maeda
发明人： Tsukasa Matoba , Takeshi Aikawa , Mitsuyoshi Okamura , Kenichi Maeda
IPC分类号： G06F12/08
CPC分类号： G06F12/0855
摘要： A copy-back type cache memory device using a delayed wait method capable of completing a data-write process in one process cycle. The device includes single word memory means for storing the single word of the selected data in a data memory means when an access for a data-write is made, the single word being located at the address in the data memory means corresponding to the processor address; and copy-back memory means for restoring the superseded data along with other data together with which the superseded data forms a block, so that the block can be reorganized in its original state before the data-write process takes place. The device may alternatively include an address latch means for delaying transmission of a processor address from the processor to the data memory means by a predetermined number of process cycles when access by the processor is for a data-write process; and a data latch means for delaying transmission of a processor data from the processor to the data memory means by the predetermined number of process cycles when access by the processor is for a data-write process.
摘要翻译：使用能够在一个处理周期中完成数据写入处理的延迟等待方法的复制型高速缓冲存储器件。该装置包括单字存储装置，用于当进行数据写入的存取时，在数据存储装置中存储所选数据的单字，该单字位于与处理器地址对应的数据存储装置中的地址处 ; 以及复制存储器装置，用于将取代的数据与其他数据一起恢复，取代的数据与其一起形成一个块，使得该块可以在数据写入过程发生之前被重新组织成其初始状态。该设备可以替代地包括地址锁存装置，用于当由处理器访问用于数据写入处理时，延迟处理器地址从处理器传输到数据存储器装置预定数量的处理周期; 以及数据锁存装置，用于当由处理器访问用于数据写入处理时，将处理器数据从处理器传输到数据存储器装置预定数量的处理周期。

5. 发明授权

US4185271A Character reading system 失效
标题翻译：字符阅读系统
公开(公告)号：US4185271A
公开(公告)日：1980-01-22
申请号：US947574
申请日：1978-10-02
申请人： Koji Izawa , Kouichi Komatsu , Mitsuyoshi Okamura
发明人： Koji Izawa , Kouichi Komatsu , Mitsuyoshi Okamura
IPC分类号： G06K9/38 , G06K9/40 , H04N1/04 , G06K9/12
CPC分类号： G06K9/40 , G06K2209/01
摘要： The character reading system is provided with a pretreating system for a pattern recognition and a picture translation wherein a pattern signal obtained by scanning a character pattern on a recording medium is processed at such high threshold level that does not contain a noise component to form a primary kernel pattern, and the pattern signal is processed at such low threshold level that contains said character pattern to obtain a reference pattern. The kernel pattern and the reference pattern are masked on a memory device to have predetermined size and subjected to connecting operation when they are read out by forward scanning to form a connected secondary kernel pattern. The secondary kernel pattern and the reference pattern are masked to have predetermined size and then reversely scanned to subject both patterns to the second connecting operation thereby producing a last kernel pattern.
摘要翻译：字符读取系统设置有用于模式识别和图像转换的预处理系统，其中通过扫描记录介质上的字符图案获得的图案信号在不包含噪声分量的高阈值水平处理以形成初级内核模式，并且模式信号在包含所述字符模式的低阈值级别处理以获得参考模式。内核模式和参考模式在存储设备上被屏蔽以具有预定的大小，并且当它们通过正向扫描读出以形成连接的二级核心模式时，进行连接操作。二次核心图案和参考图案被掩蔽以具有预定尺寸，然后反向扫描以将两个图案对准第二连接操作，从而产生最后的核心图案。

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