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1. 发明申请

US20070061657A1 Delay fault testing apparatus 审中-公开
标题翻译：延时故障测试仪
公开(公告)号：US20070061657A1
公开(公告)日：2007-03-15
申请号：US11203381
申请日：2005-08-12
申请人： Tsin-Yuan Chang , Po-Lin Chen , Hao-Hsuan Chiu
发明人： Tsin-Yuan Chang , Po-Lin Chen , Hao-Hsuan Chiu
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31858
摘要： A delay fault testing apparatus includes a scan device having a first input for receiving a data to the core under test, an update device including an input electrically connected to a first output of the scan device, a first multiplexer including a first input electrically connected to the output of the scan device, a second input electrically connected to a first output of the update device, and an output electrically connected to an input of the core under test. The first input of the first multiplexer is switched to the output when a first control signal is asserted so that the output of the scan device is allowed to directly connect to the output of the first multiplexer to launch a transition by switching the first multiplexer rather than triggering an update event, which is restricted to be triggered in the time of a negative edge.
摘要翻译：一种延迟故障测试装置包括：扫描装置，具有用于向被测核心接收数据的第一输入端，包括电连接到扫描装置的第一输出端的输入端的更新装置;第一多路复用器，包括电连接到扫描装置的输出，电连接到更新装置的第一输出的第二输入，以及电连接到被测核心的输入的输出。当第一控制信号被断言时，第一多路复用器的第一输入被切换到输出，使得允许扫描装置的输出直接连接到第一多路复用器的输出，以通过切换第一多路复用器来发射转换，而不是触发一个更新事件，这个更新事件被限制为在一个负边缘的时间被触发。

2. 发明申请

US20050024120A1 Method and apparatus for controlling a dual-slope integrator circuit to eliminate settling time effect 有权
标题翻译：用于控制双斜率积分器电路以消除稳定时间效应的方法和装置
公开(公告)号：US20050024120A1
公开(公告)日：2005-02-03
申请号：US10748580
申请日：2003-12-30
申请人： Tsin-Yuan Chang , Ming-Jun Hsiao , Jing-Reng Huang
发明人： Tsin-Yuan Chang , Ming-Jun Hsiao , Jing-Reng Huang
IPC分类号： G06F5/00 , G06G7/18 , G06G7/186 , H03K4/00 , H03K4/06 , H03K5/1534
CPC分类号： G06G7/186 , H03K4/066 , H03K5/1534
摘要： In a method and apparatus for controlling a dual-slope integrator circuit, a reset signal is provided to a reset input of the integrator circuit to maintain a reset state of an integrating capacitor for a predetermined reset time period in response to an original input signal. A delayed input signal is simultaneously generated by introducing a predetermined delay period into the original input signal, the delay period being longer than the reset time period. With reference to the original input signal and the delayed input signal, a trigger signal is provided to an integrator input of the integrator circuit for enabling charging operation of the integrating capacitor during a charging period that starts from the end of the reset time period and that terminates at a lagging edge of the delayed input signal.
摘要翻译：在用于控制双斜率积分器电路的方法和装置中，响应于原始输入信号，将复位信号提供给积分器电路的复位输入，以将积分电容器的复位状态保持在预定复位时间段。通过将预定的延迟周期引入原始输入信号中，延迟输入信号同时产生，延迟时间长于复位时间段。参考原始输入信号和延迟输入信号，将触发信号提供给积分器电路的积分器输入，用于在从复位时间段结束开始的充电期间内对积分电容器进行充电操作，在延迟输入信号的滞后沿终止。

3. 发明授权

US06914471B2 Method and apparatus for controlling a dual-slope integrator circuit to eliminate settling time effect 有权
公开(公告)号：US06914471B2
公开(公告)日：2005-07-05
申请号：US10748580
申请日：2003-12-30
申请人： Tsin-Yuan Chang , Ming-Jun Hsiao , Jing-Reng Huang
发明人： Tsin-Yuan Chang , Ming-Jun Hsiao , Jing-Reng Huang
IPC分类号： G06F5/00 , G06G7/18 , G06G7/186 , H03K4/00 , H03K4/06 , H03K5/1534
CPC分类号： G06G7/186 , H03K4/066 , H03K5/1534
摘要： In a method and apparatus for controlling a dual-slope integrator circuit, a reset signal is provided to a reset input of the integrator circuit to maintain a reset state of an integrating capacitor for a predetermined reset time period in response to an original input signal. A delayed input signal is simultaneously generated by introducing a predetermined delay period into the original input signal, the delay period being longer than the reset time period. With reference to the original input signal and the delayed input signal, a trigger signal is provided to an integrator input of the integrator circuit for enabling charging operation of the integrating capacitor during a charging period that starts from the end of the reset time period and that terminates at a lagging edge of the delayed input signal.

4. 发明授权

US06873557B2 Integrated circuit device with a built-in detecting circuit for detecting maximum memory access time of an embedded memory 失效
标题翻译：具有内置检测电路的集成电路器件，用于检测嵌入式存储器的最大存储器访问时间
公开(公告)号：US06873557B2
公开(公告)日：2005-03-29
申请号：US10601709
申请日：2003-06-19
申请人： Tsin-Yuan Chang , Ming-Jun Hsiao , Shu-Rong Lee
发明人： Tsin-Yuan Chang , Ming-Jun Hsiao , Shu-Rong Lee
IPC分类号： G11C29/50 , G11C7/00
CPC分类号： G11C29/50012 , G11C29/50 , G11C2207/104
摘要： An integrated circuit device includes an embedded memory, a built-in self-test (BIST) circuit, an access time measuring circuit, and a built-in detecting circuit. The BIST circuit is coupled electrically to the memory, and is operable so as to perform consecutive test operations upon addressable memory locations of the memory. The access time measuring circuit is coupled electrically to the memory and the BIST circuit, and is operable so as to generate an access time signal corresponding to access time of one of the memory locations that is currently being tested by the BIST circuit. The detecting circuit is coupled electrically to the measuring circuit, monitors a maximum value of the access time signals generated by the measuring circuit during the consecutive test operations, and outputs a maximum access time signal upon completion of the consecutive test operations.
摘要翻译：集成电路装置包括嵌入式存储器，内置自检（BIST）电路，存取时间测量电路和内置检测电路。 BIST电路电耦合到存储器，并且可操作以便在存储器的可寻址存储器位置上执行连续的测试操作。访问时间测量电路电连接到存储器和BIST电路，并且可操作以产生对应于当前正被BIST电路测试的存储器位置之一的访问时间的访问时间信号。检测电路与测量电路电连接，在连续测试操作期间监视由测量电路产生的存取时间信号的最大值，并在连续测试操作完成时输出最大存取时间信号。

5. 发明授权

US06791387B1 Feedback latch circuit and method therefor 有权
标题翻译：反馈锁存电路及其方法
公开(公告)号：US06791387B1
公开(公告)日：2004-09-14
申请号：US10650368
申请日：2003-08-27
申请人： Tsin-Yuan Chang , Hao-Yung Lo , Shao-Sheng Yang
发明人： Tsin-Yuan Chang , Hao-Yung Lo , Shao-Sheng Yang
IPC分类号： H03K3037
CPC分类号： H03K3/037 , H03K3/012
摘要： A feedback latch circuit includes a first logic OR gate for performing a logic OR operation upon a clock input signal and a latch output, a first logic AND gate for performing a logic AND operation upon output of the first logic OR gate and a data input signal, a second logic AND gate for performing a logic AND operation upon a complementary clock input signal and the latch output, and a second logic OR gate for performing a logic OR operation upon outputs of the first and second logic AND gates to result in the latch output that is provided to the first logic OR gate and the second logic AND gate. The complementary clock input signal received by the second logic AND gate complements the clock input signal received by the first logic OR gate.
摘要翻译：反馈锁存电路包括用于在时钟输入信号和锁存器输出端执行逻辑或运算的第一逻辑“或”门，用于在第一逻辑或门输出时执行逻辑与运算的第一逻辑与门和数据输入信号，用于对互补时钟输入信号和所述锁存器输出执行逻辑与运算的第二逻辑与门，以及用于在所述第一和第二逻辑与门的输出上执行逻辑或运算以产生所述锁存器的第二逻辑或门输出提供给第一逻辑或门和第二逻辑与门。由第二逻辑与门接收的互补时钟输入信号补充由第一逻辑或门接收的时钟输入信号。

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