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1. 发明申请

US20100006954A1 TRANSISTOR DEVICE 审中-公开
标题翻译：晶体管器件
公开(公告)号：US20100006954A1
公开(公告)日：2010-01-14
申请号：US12241096
申请日：2008-09-30
申请人： Tsai-Yu Huang , Shin-Yu Nieh , Hui-Lan Chang
发明人： Tsai-Yu Huang , Shin-Yu Nieh , Hui-Lan Chang
IPC分类号： H01L29/78
CPC分类号： H01L29/517 , H01L21/0214 , H01L21/02148 , H01L21/02164 , H01L21/02181 , H01L21/02274 , H01L21/0228 , H01L21/02356 , H01L21/28017 , H01L21/28202 , H01L21/28211 , H01L21/3141 , H01L21/3144 , H01L21/31612 , H01L21/31645
摘要： A transistor device includes a semiconductor substrate, a source doping region and a drain doping region in the semiconductor, a channel region between the source doping region and the drain doping region, a gate stack on the channel region, wherein the gate stack includes an amorphous interfacial layer, a crystalline metal oxide gate dielectric layer and a gate conductor.
摘要翻译：晶体管器件包括半导体衬底，源极掺杂区域和半导体中的漏极掺杂区域，源极掺杂区域和漏极掺杂区域之间的沟道区域，沟道区域上的栅极堆叠，其中栅极堆叠包括无定形的界面层，结晶金属氧化物栅极电介质层和栅极导体。

2. 发明申请

US20100172065A1 CAPACITOR STRUCTURE 审中-公开
标题翻译：电容结构
公开(公告)号：US20100172065A1
公开(公告)日：2010-07-08
申请号：US12399020
申请日：2009-03-06
申请人： Tsai-Yu Huang , Shin-Yu Nieh , Hui-Lan Chang
发明人： Tsai-Yu Huang , Shin-Yu Nieh , Hui-Lan Chang
IPC分类号： H01G4/20
CPC分类号： H01G4/10 , H01G4/105 , H01G4/33 , H01L28/40
摘要： A capacitor structure includes: a top electrode, a bottom electrode, a first capacitor dielectric layer positioned between the top electrode and the bottom electrode and a second capacitor dielectric layer positioned between the top electrode and the bottom electrode. The first capacitor dielectric layer is selected from the group consisting HfO2, ZrO2, and TiO2. The second capacitor dielectric layer is selected from the group consisting of lanthanide oxide series and rare earth oxide series.
摘要翻译：电容器结构包括：顶电极，底电极，位于顶电极和底电极之间的第一电容器电介质层和位于顶电极和底电极之间的第二电容介电层。第一电容器介电层选自HfO 2，ZrO 2和TiO 2。第二电容器电介质层选自镧系元素氧化物系列和稀土氧化物系列。

3. 发明授权

US08043884B1 Methods of seamless gap filling 有权
标题翻译：无缝填充方法
公开(公告)号：US08043884B1
公开(公告)日：2011-10-25
申请号：US12786249
申请日：2010-05-24
申请人： Shin-Yu Nieh , Shuo-Che Chang , Hui-Lan Chang , Cheng-Shun Chen
发明人： Shin-Yu Nieh , Shuo-Che Chang , Hui-Lan Chang , Cheng-Shun Chen
IPC分类号： H01L21/00
CPC分类号： H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/0228 , H01L21/76232
摘要： A method for seamless gap filling is provided, including providing a semiconductor structure with a device layer having a gap therein, wherein the gap has an aspect ratio greater than 4. A liner layer is formed over the device layer exposed by the gap. A first un-doped oxide layer is formed over the liner layer in the gap. A doped oxide layer is formed over the first undoped oxide layer in the gap. A second un-doped oxide layer is formed over the doped oxide layer in the gap to fill the gap. An annealing process is performed on the second un-doped oxide layer, the doped oxide layer, and the first un-doped oxide to form a seamless oxide layer in the gap, wherein the seamless oxide layer has an interior doped region.
摘要翻译：提供了一种用于无缝间隙填充的方法，包括提供具有在其中具有间隙的器件层的半导体结构，其中间隙具有大于4的纵横比。在由间隙暴露的器件层上形成衬垫层。在间隙中的衬垫层上形成第一未掺杂氧化物层。在间隙中的第一未掺杂氧化物层上形成掺杂的氧化物层。在间隙中的掺杂氧化物层上形成第二未掺杂氧化物层以填充间隙。对第二未掺杂氧化物层，掺杂氧化物层和第一未掺杂氧化物进行退火处理，以在间隙中形成无缝氧化物层，其中无缝氧化物层具有内部掺杂区域。

4. 发明申请

US20090283856A1 METHOD FOR FABRICATING A SEMICONDUCTOR CAPACITPR DEVICE 审中-公开
标题翻译：制备半导体CAPACITPR器件的方法
公开(公告)号：US20090283856A1
公开(公告)日：2009-11-19
申请号：US12167239
申请日：2008-07-02
申请人： Tsai-Yu Huang , Shin-Yu Nieh , Chun-I Hsieh
发明人： Tsai-Yu Huang , Shin-Yu Nieh , Chun-I Hsieh
IPC分类号： H01L29/94
CPC分类号： H01L28/40 , H01L28/60 , H01L28/75
摘要： A method for fabricating a semiconductor capacitor includes a substrate having thereon a carbon electrode. A transitional barrier layer is then deposited on the carbon electrode layer. Thereafter, a metal oxide layer is deposited on the transitional barrier layer, which reacts with the underlying transitional barrier layer to form a metal oxy-nitride layer acting as a capacitor dielectric layer of the capacitor device. A top electrode layer is then formed on the metal oxy-nitride layer.
摘要翻译：一种制造半导体电容器的方法包括其上具有碳电极的基板。然后在碳电极层上沉积过渡阻挡层。此后，金属氧化物层沉积在过渡阻挡层上，其与下面的过渡阻挡层反应，形成用作电容器器件的电容器电介质层的金属氧化氮层。然后在金属氮氧化物层上形成顶部电极层。

5. 发明申请

US20090311878A1 METHOD FOR DEPOSITING A DIELECTRIC MATERIAL 审中-公开
标题翻译：沉积介电材料的方法
公开(公告)号：US20090311878A1
公开(公告)日：2009-12-17
申请号：US12198715
申请日：2008-08-26
申请人： Shin-Yu Nieh , Tsai-Yu Huang , Chun-I Hsieh
发明人： Shin-Yu Nieh , Tsai-Yu Huang , Chun-I Hsieh
IPC分类号： H01L21/31
CPC分类号： H01L21/31645 , C23C16/40 , C23C16/45531 , C23C16/45553 , H01L21/02145 , H01L21/02148 , H01L21/02159 , H01L21/0228 , H01L21/3141 , H01L21/3162 , H01L21/31641
摘要： A depositing method for a dielectric material is provided, where the dielectric material has the first and the second primary elements, and a single precursor includes the first and the second primary elements. The depositing method includes pulsing the single precursor, purging a redundant part of the single precursor, pulsing an oxidant for oxidizing the single precursor, and purging a redundant part of the oxidant.
摘要翻译：提供了一种用于介电材料的沉积方法，其中电介质材料具有第一和第二主要元件，单个前体包括第一和第二主要元件。沉积方法包括脉冲单一前体，清洗单一前体的冗余部分，脉冲氧化剂氧化单一前体，以及清除氧化剂的多余部分。

6. 发明申请

US20100310790A1 METHOD OF FORMING CARBON-CONTAINING LAYER 审中-公开
标题翻译：形成含碳层的方法
公开(公告)号：US20100310790A1
公开(公告)日：2010-12-09
申请号：US12480693
申请日：2009-06-09
申请人： Shuo-Che Chang , Shin-Yu Nieh
发明人： Shuo-Che Chang , Shin-Yu Nieh
IPC分类号： B05D3/00
CPC分类号： C23C16/26 , B05D1/62 , B05D5/083
摘要： A method of forming a carbon-containing layer is provided. First, a substrate having a target layer thereon is provided. Next, a plasma containing CxHyFz is generated. Thereafter, a plasma deposition process is performed to the substrate by using the plasma containing CxHyFz so as to form the carbon-containing layer on the target layer.
摘要翻译：提供了形成含碳层的方法。首先，提供其上具有靶层的基板。接下来，生成含有CxHyFz的等离子体。此后，通过使用含有CxHyFz的等离子体对基板进行等离子体沉积处理，以在目标层上形成含碳层。

7. 发明申请

US20130337629A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130337629A1
公开(公告)日：2013-12-19
申请号：US13523912
申请日：2012-06-15
申请人： Tieh-Chiang Wu , Wei-Ming Liao , Jei-Cheng Huang , Shin-Yu Nieh
发明人： Tieh-Chiang Wu , Wei-Ming Liao , Jei-Cheng Huang , Shin-Yu Nieh
IPC分类号： H01L21/02
CPC分类号： H01L29/66181 , H01L27/0629 , H01L27/108 , H01L27/10861 , H01L29/945
摘要： A method of fabricating a semiconductor device is described. A substrate having first and second areas is provided. A first patterned mask layer having at least one first opening in the first area and at least one second opening in the second area is formed over the substrate, wherein the first opening is smaller than the second opening. A portion of the substrate is removed with the first patterned mask layer as a mask to form first and second trenches respectively in the substrate in the first and second areas, wherein the width and the depth of the first trench are less than those of the second trench. A first dielectric layer is formed at least in the first and second trenches. A conductive structure is formed on the first dielectric layer on at least a portion of the sidewall of each of the first and second trenches.
摘要翻译：描述制造半导体器件的方法。提供具有第一和第二区域的基板。第一图案化掩模层在第一区域中具有至少一个第一开口和第二区域中的至少一个第二开口形成在衬底上，其中第一开口小于第二开口。用第一图案化掩模层作为掩模去除衬底的一部分，以分别在第一和第二区域中的衬底中形成第一和第二沟槽，其中第一沟槽的宽度和深度小于第二沟槽的宽度和深度沟。至少在第一和第二沟槽中形成第一介电层。在所述第一和第二沟槽中的每一个的侧壁的至少一部分上的第一介电层上形成导电结构。

8. 发明授权

US08183614B2 Stack capacitor of memory device and fabrication method thereof 有权
标题翻译：存储器件的堆叠电容器及其制造方法
公开(公告)号：US08183614B2
公开(公告)日：2012-05-22
申请号：US13294937
申请日：2011-11-11
申请人： Shin-Yu Nieh
发明人： Shin-Yu Nieh
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/90 , H01L27/1085
摘要： The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.
摘要翻译：本发明提供了一种用于形成存储器件的堆叠电容器的方法，包括提供衬底，在衬底上形成具有多个第一开口的图案化牺牲层，在图案化的牺牲层上和第一层中共形地形成第一导电层开口，在第一导电层上形成第二导电层，以密封其中形成的空隙的第一开口，去除第一和第二导电层的一部分以暴露图案化的牺牲层，以及去除图案化牺牲层的至少一部分层形成底细胞板。

9. 发明授权

US08084323B2 Stack capacitor of memory device and fabrication method thereof 有权
标题翻译：存储器件的堆叠电容器及其制造方法
公开(公告)号：US08084323B2
公开(公告)日：2011-12-27
申请号：US12640846
申请日：2009-12-17
申请人： Shin-Yu Nieh
发明人： Shin-Yu Nieh
IPC分类号： H01L21/8242
CPC分类号： H01L28/90 , H01L27/1085
摘要： The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.
摘要翻译：本发明提供了一种用于形成存储器件的堆叠电容器的方法，包括提供衬底，在衬底上形成具有多个第一开口的图案化牺牲层，在图案化的牺牲层上和第一层中共形形成第一导电层开口，在第一导电层上形成第二导电层，以密封其中形成的空隙的第一开口，去除第一和第二导电层的一部分以暴露图案化的牺牲层，以及去除图案化牺牲层的至少一部分层形成底细胞板。

10. 发明授权

US08912065B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08912065B2
公开(公告)日：2014-12-16
申请号：US13523912
申请日：2012-06-15
申请人： Tieh-Chiang Wu , Wei-Ming Liao , Jei-Cheng Huang , Shin-Yu Nieh
发明人： Tieh-Chiang Wu , Wei-Ming Liao , Jei-Cheng Huang , Shin-Yu Nieh
IPC分类号： H01L21/336
CPC分类号： H01L29/66181 , H01L27/0629 , H01L27/108 , H01L27/10861 , H01L29/945
摘要： A method of fabricating a semiconductor device is described. A substrate having first and second areas is provided. A first patterned mask layer having at least one first opening in the first area and at least one second opening in the second area is formed over the substrate, wherein the first opening is smaller than the second opening. A portion of the substrate is removed with the first patterned mask layer as a mask to form first and second trenches respectively in the substrate in the first and second areas, wherein the width and the depth of the first trench are less than those of the second trench. A first dielectric layer is formed at least in the first and second trenches. A conductive structure is formed on the first dielectric layer on at least a portion of the sidewall of each of the first and second trenches.
摘要翻译：描述制造半导体器件的方法。提供具有第一和第二区域的基板。第一图案化掩模层在第一区域中具有至少一个第一开口和第二区域中的至少一个第二开口形成在衬底上，其中第一开口小于第二开口。用第一图案化掩模层作为掩模去除衬底的一部分，以分别在第一和第二区域中的衬底中形成第一和第二沟槽，其中第一沟槽的宽度和深度小于第二沟槽的宽度和深度沟。至少在第一和第二沟槽中形成第一电介质层。在所述第一和第二沟槽中的每一个的侧壁的至少一部分上的第一介电层上形成导电结构。

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