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1. 发明授权

US07706363B1 Method and apparatus for managing packets in a packet switched network 有权
标题翻译：用于在分组交换网络中管理分组的方法和装置
公开(公告)号：US07706363B1
公开(公告)日：2010-04-27
申请号：US10829866
申请日：2004-04-21
申请人： Tsahi Daniel , Donald Pannell , Nafea Bishara , Yuval Cohen
发明人： Tsahi Daniel , Donald Pannell , Nafea Bishara , Yuval Cohen
IPC分类号： H04L12/28
CPC分类号： H04L12/4625 , H04L12/4645 , H04L49/354 , H04L49/45
摘要： Method and apparatus for modifying standard VLAN tags to perform network packet switching. The method includes receiving a data packet at a port of a network switch and determining whether the data packet has a virtual local area network (VLAN) tagged frame. If the received data packet has a VLAN tagged frame, then the method further includes modifying and encoding fixed portions of the VLAN tag frame with switching information. The switching information includes information for central management of data packet flow through the network switch.
摘要翻译：修改标准VLAN标签以执行网络分组交换的方法和装置。该方法包括在网络交换机的端口处接收数据分组，并确定数据分组是否具有标记有虚拟局域网（VLAN）的帧。如果接收到的数据包具有VLAN标签帧，则该方法还包括修改和编码具有切换信息的VLAN标签帧的固定部分。切换信息包括用于通过网络交换机的数据分组流的中央管理的信息。

2. 发明授权

US08923297B1 Method and apparatus for managing packets in a packet switched network 有权
标题翻译：用于在分组交换网络中管理分组的方法和装置
公开(公告)号：US08923297B1
公开(公告)日：2014-12-30
申请号：US13415557
申请日：2012-03-08
申请人： Tsahi Daniel , Donald Pannell , Nafea Bishara , Yuval Cohen
发明人： Tsahi Daniel , Donald Pannell , Nafea Bishara , Yuval Cohen
IPC分类号： H04L12/28
CPC分类号： H04L12/4625 , H04L12/4645 , H04L49/354 , H04L49/45
摘要： Methods and apparatus for managing packets in a packet switched network include, in at least one aspect, a device including: an input to receive a packet from one of a plurality of network devices, the plurality of network devices configured to communicate with one or more others of the network devices using a plurality of packets; and circuitry configured to control packet switching of the plurality of packets, at least one packet including: a switch tag including a tag portion embedded with switching information and an extended tag portion embedded with additional switching information, the switching information and the additional switching information configured to control a switching pattern associated with the at least one packet.
摘要翻译：在分组交换网络中用于管理分组的方法和装置在至少一个方面包括：设备，包括：用于从多个网络设备之一接收分组的输入，所述多个网络设备被配置为与一个或多个使用多个分组的其他网络设备; 以及电路，被配置为控制所述多个分组的分组交换，所述至少一个分组包括：包括嵌入有交换信息的标签部分的交换标签和嵌入有附加切换信息的扩展标签部分，所述切换信息和所述附加切换信息被配置以控制与所述至少一个分组相关联的切换模式。

3. 发明授权

US08144706B1 Method and apparatus for managing packets in a packet switched network 有权
标题翻译：用于在分组交换网络中管理分组的方法和装置
公开(公告)号：US08144706B1
公开(公告)日：2012-03-27
申请号：US12753808
申请日：2010-04-02
申请人： Tsahi Daniel , Donald Pannell , Nafea Bishara , Yuval Cohen
发明人： Tsahi Daniel , Donald Pannell , Nafea Bishara , Yuval Cohen
IPC分类号： H04L12/28
CPC分类号： H04L12/4625 , H04L12/4645 , H04L49/354 , H04L49/45
摘要： Systems, methods, and computer program products for modifying standard VLAN tags to perform network packet switching are described. In some implementations, a data packet can be received, and the data format of the data packet can be determined. Then, switching information associated with data package management is generated based on the data format of the data packet. The data packet can be modified using the generated switching information. For example, the modified data packet can be extended by a predetermined length to accommodate additional switching information.
摘要翻译：描述了用于修改标准VLAN标签以执行网络分组交换的系统，方法和计算机程序产品。在一些实现中，可以接收数据分组，并且可以确定数据分组的数据格式。然后，基于数据包的数据格式生成与数据包管理相关联的切换信息。可以使用生成的切换信息来修改数据分组。例如，修改的数据分组可以扩展预定长度以适应附加的切换信息。

4. 发明授权

US09584342B1 Enhanced audio video bridging (AVB) methods and apparatus 有权
标题翻译：增强音视频桥接（AVB）方法和设备
公开(公告)号：US09584342B1
公开(公告)日：2017-02-28
申请号：US13115868
申请日：2011-05-25
申请人： Donald Pannell
发明人： Donald Pannell
IPC分类号： H04L12/46 , H04L12/54 , H04L12/913
CPC分类号： H04L49/354 , H04J3/16 , H04L12/28 , H04L12/462 , H04L12/56 , H04L45/745 , H04L45/7453 , H04L47/24 , H04L47/2408 , H04L47/245 , H04L47/2458 , H04L47/6215 , H04L47/70 , H04L47/724 , H04L49/201 , H04L49/3027 , H04L49/90 , H04L2012/5638
摘要： A packet is received via a port of the network device, and a database lookup is performed using header information of the packet. A priority associated with the packet is determined, and it is determined whether the priority is associated with a particular communication protocol that provides guaranteed delivery, defined latency, and/or defined throughput. When it is determined that the priority is associated with the particular communication protocol, i) it is determined, based on the database lookup, whether a destination address (DA) of the packet is associated with the particular communication protocol, and ii) when it is determined that the DA of the packet is associated with the particular communication protocol, the packet is prevented from egressing from ports of the network device that are operating according to the particular communication protocol with a frame priority indicator corresponding to a value reserved for the particular communication protocol.
摘要翻译：通过网络设备的端口接收分组，并且使用分组的报头信息来执行数据库查找。确定与分组相关联的优先级，并且确定优先级是否与提供保证传递，定义的等待时间和/或定义的吞吐量的特定通信协议相关联。当确定优先级与特定通信协议相关联时，i）基于数据库查找确定分组的目的地地址（DA）是否与特定通信协议相关联，以及ii）何时确定分组的DA与特定通信协议相关联，防止分组从根据特定通信协议操作的网络设备的端口出来，其中帧优先级指示符对应于为特定通信协议保留的值通讯协议。

5. 发明授权

US08705416B2 Duplex mismatch detection 有权
标题翻译：双工不匹配检测
公开(公告)号：US08705416B2
公开(公告)日：2014-04-22
申请号：US13315800
申请日：2011-12-09
申请人： Donald Pannell , Ozdal Barkan
发明人： Donald Pannell , Ozdal Barkan
IPC分类号： H04B1/44
CPC分类号： H04L5/14
摘要： An apparatus including a port to transmit first frames and receive second frames over a communication channel, the port including a collision detect circuit and a duplex mismatch circuit. The collision detect circuit detects collisions on the communication channel between the first frames and the second frames. The duplex mismatch circuit declares a duplex mismatch when the communication channel was established without attempting auto-negotiation, the port is in a half-duplex mode, and the collision detect circuit detects a very late collision involving one of the first frames. The very late collision occurs after a predetermined amount of data has been transmitted in the one of the first frames. The duplex mismatch indicates that a full-duplex mode is used with respect to the second frames.
摘要翻译：一种装置，包括用于发送第一帧并通过通信信道接收第二帧的端口，所述端口包括冲突检测电路和双工不匹配电路。冲突检测电路检测第一帧和第二帧之间的通信信道上的冲突。当通信信道建立而不尝试自动协商，端口处于半双工模式，并且冲突检测电路检测到涉及其中一个第一帧的非常晚的冲突时，双工不匹配电路声明双工不匹配。在第一帧之一中发送预定量的数据之后发生非常晚的冲突。双工不匹配表示相对于第二帧使用全双工模式。

6. 发明授权

US08335878B2 Multiport memory architecture, devices and systems including the same, and methods of using the same 有权
标题翻译：多端口存储器架构，包括相同的器件和系统以及使用它们的方法
公开(公告)号：US08335878B2
公开(公告)日：2012-12-18
申请号：US12494076
申请日：2009-06-29
申请人： Winston Lee , Sehat Sutardja , Donald Pannell
发明人： Winston Lee , Sehat Sutardja , Donald Pannell
IPC分类号： G06F7/00 , G11C11/401
CPC分类号： G11C7/1075
摘要： A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses.
摘要翻译：多端口内存架构，系统包括相同以及使用方法。架构通常包括（a）存储器阵列; （b）配置成接收和/或发送数据的多个端口; 以及（c）多个端口缓冲器，每个端口缓冲器被配置为从一个或多个端口发送数据和/或从一个或多个端口接收数据，并且所有端口缓冲器被配置为（i）将数据发送到存储器阵列在第一公共总线上，（ii）在第二公共总线上从存储器阵列接收数据。系统通常包括体现本文公开的一个或多个发明构思的系统。所述方法通常涉及将数据块写入到数据块，从存储器读取数据块和/或传送数据块。本发明有利地通过将端口缓冲器紧密地耦合到主存储器并且有利地使用存储器读写路径的长段上的点对点通信来减少数据通信中的特别是网络交换机中的等待时间，从而减少路由拥塞和启用消除FIFO。本发明有利地缩小芯片尺寸并提供增加的数据传输速率和吞吐量，并且在优选实施例中，存储器读和写总线中的电阻和/或电容减小。

7. 发明申请

US20120076057A1 Duplex Mismatch Detection 有权
标题翻译：双工不匹配检测
公开(公告)号：US20120076057A1
公开(公告)日：2012-03-29
申请号：US13315800
申请日：2011-12-09
申请人： Donald Pannell , Ozdal Barkan
发明人： Donald Pannell , Ozdal Barkan
IPC分类号： H04L5/14 , H04L5/16
CPC分类号： H04L5/14
摘要： An apparatus including a port to transmit first frames and receive second frames over a communication channel, the port including a collision detect circuit and a duplex mismatch circuit. The collision detect circuit detects collisions on the communication channel between the first frames and the second frames. The duplex mismatch circuit declares a duplex mismatch when the communication channel was established without attempting auto-negotiation, the port is in a half-duplex mode, and the collision detect circuit detects a very late collision involving one of the first frames. The very late collision occurs after a predetermined amount of data has been transmitted in the one of the first frames. The duplex mismatch indicates that a full-duplex mode is used with respect to the second frames.
摘要翻译：一种装置，包括用于发送第一帧并通过通信信道接收第二帧的端口，所述端口包括冲突检测电路和双工不匹配电路。冲突检测电路检测第一帧和第二帧之间的通信信道上的冲突。当通信信道建立而不尝试自动协商，端口处于半双工模式，并且冲突检测电路检测到涉及其中一个第一帧的非常晚的冲突时，双工不匹配电路声明双工不匹配。在第一帧之一中发送预定量的数据之后发生非常晚的冲突。双工不匹配表示相对于第二帧使用全双工模式。

8. 发明授权

US07571287B2 Multiport memory architecture, devices and systems including the same, and methods of using the same 有权
标题翻译：多端口存储器架构，包括相同的器件和系统以及使用它们的方法
公开(公告)号：US07571287B2
公开(公告)日：2009-08-04
申请号：US10702744
申请日：2003-11-05
申请人： Winston Lee , Sehat Sutardja , Donald Pannell
发明人： Winston Lee , Sehat Sutardja , Donald Pannell
IPC分类号： G06F12/00
CPC分类号： G11C7/1075
摘要： A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses.
摘要翻译：多端口内存架构，系统包括相同以及使用方法。架构通常包括（a）存储器阵列; （b）配置成接收和/或发送数据的多个端口; 以及（c）多个端口缓冲器，每个端口缓冲器被配置为从一个或多个端口发送数据和/或从一个或多个端口接收数据，并且所有端口缓冲器被配置为（i）将数据发送到存储器阵列在第一公共总线上，（ii）在第二公共总线上从存储器阵列接收数据。系统通常包括体现本文公开的一个或多个发明构思的系统。所述方法通常涉及将数据块写入到数据块，从存储器读取数据块和/或传送数据块。本发明有利地通过将端口缓冲器紧密地耦合到主存储器并且有利地使用存储器读写路径的长段上的点对点通信来减少数据通信中的特别是网络交换机中的等待时间，从而减少路由拥塞和启用消除FIFO。本发明有利地缩小芯片尺寸并提供增加的数据传输速率和吞吐量，并且在优选实施例中，存储器读和写总线中的电阻和/或电容减小。

9. 发明授权

US09590910B1 Methods and apparatus for handling multicast packets in an audio video bridging (AVB) network 有权
标题翻译：用于在音频视频桥接（AVB）网络中处理多播分组的方法和装置
公开(公告)号：US09590910B1
公开(公告)日：2017-03-07
申请号：US13115670
申请日：2011-05-25
申请人： Donald Pannell
发明人： Donald Pannell
IPC分类号： H04L12/743 , H04L12/931 , H04L12/851
CPC分类号： H04L49/354 , H04J3/16 , H04L12/28 , H04L12/462 , H04L12/56 , H04L45/745 , H04L45/7453 , H04L47/24 , H04L47/2408 , H04L47/245 , H04L47/2458 , H04L47/6215 , H04L47/70 , H04L47/724 , H04L49/201 , H04L49/3027 , H04L49/90 , H04L2012/5638
摘要： It is determined whether a packet is a multicast packet, and an index to a database is selected from i) a first candidate index determined based on header information of the packet, or ii) a second candidate index determined based on the header information, based on whether the packet is a multicast packet. Information is retrieved from the database using the index, and the header information is compared with information retrieved from the database. Further information retrieved from the database is used to determine one or more ports via which the packet should be transmitted when the header information matches the information retrieved from the database.
摘要翻译：确定分组是否是多播分组，并且从i）基于分组的报头信息确定的第一候选索引选择数据库的索引，或者ii）基于标题信息确定的第二候选索引关于数据包是否是组播数据包。使用索引从数据库检索信息，并将标题信息与从数据库检索的信息进行比较。从数据库检索的更多信息用于确定一个或多个端口，当头部信息与从数据库检索到的信息匹配时，通过该端口发送数据包。

10. 发明授权

US09229518B1 Wake-on-frame for frame processing devices 有权
标题翻译：帧处理设备的唤醒功能
公开(公告)号：US09229518B1
公开(公告)日：2016-01-05
申请号：US12916968
申请日：2010-11-01
申请人： Donald Pannell , Hong Yu Chou
发明人： Donald Pannell , Hong Yu Chou
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3209 , G06F1/3287
摘要： Systems, methods, and other embodiments associated with wake-on-frame mechanisms are described. According to one embodiment, an apparatus includes a packet source configured to send packets to a frame processing device and a wake-on-frame mechanism that is selectable by the frame processing device between an enabled state and a disabled state. If the wake-on-frame mechanism is in the enabled state, a packet source that has a frame to send to the frame processing device sends a wake signal to the frame processing device prior to sending the packet. The packet source sends the packet to the frame processing device after receiving a ready signal from the frame processing device.
摘要翻译：描述了与唤醒帧机制相关联的系统，方法和其他实施例。根据一个实施例，一种装置包括被配置为向帧处理设备发送分组的分组源和在启用状态和禁用状态之间可由帧处理设备选择的唤醒帧机制。如果唤醒帧机制处于使能状态，则具有要发送到帧处理设备的帧的分组源在发送分组之前向帧处理设备发送唤醒信号。在从帧处理设备接收到就绪信号之后，分组源将该分组发送到帧处理设备。

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