专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140060027A1 SYSTEMS AND METHODS FOR REDUCING DEAD VOLUME IN COMPRESSED-GAS ENERGY STORAGE SYSTEMS 审中-公开
标题翻译：压缩能源储存系统中减少死亡体积的系统和方法
公开(公告)号：US20140060027A1
公开(公告)日：2014-03-06
申请号：US14063411
申请日：2013-10-25
申请人： Troy O. McBride , Benjamin R. Bollinger , John P. McCormick , Benjamin Cameron
发明人： Troy O. McBride , Benjamin R. Bollinger , John P. McCormick , Benjamin Cameron
IPC分类号： F15B15/02
CPC分类号： F15B15/02 , F17C1/00 , Y02E20/14 , Y10T137/86187
摘要： In various embodiments, dead space and associated coupling losses are reduced in energy storage and recovery systems employing compressed air.
摘要翻译：在各种实施例中，在使用压缩空气的能量储存和回收系统中减少了死空间和相关耦合损耗。

2. 发明授权

US06943446B2 Via construction for structural support 有权
标题翻译：通过结构支持施工
公开(公告)号：US06943446B2
公开(公告)日：2005-09-13
申请号：US10290953
申请日：2002-11-08
申请人： John P. McCormick , Ivor G. Barber , Kumar Nagarajan
发明人： John P. McCormick , Ivor G. Barber , Kumar Nagarajan
IPC分类号： H01L21/768 , H01L23/00 , H01L23/522 , H01L23/532 , H01L23/58 , H01L23/34 , H01L23/48 , H01L23/52
CPC分类号： H01L23/585 , H01L21/76877 , H01L23/5226 , H01L23/5329 , H01L23/562 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/83102 , H01L2224/92125 , H01L2924/01019 , H01L2224/05647 , H01L2924/00014
摘要： An integrated circuit having electrically conductive vias with a diameter of between about one micron and about fifty microns. Prior art vias have a diameter of between no less than 0.3 microns to no more than 0.8 microns. In this manner, stresses such as those that press down upon the top surface of the integrated circuit can be absorbed by the large vias and transferred past fragile layers, such as low k layers, so that the fragile layers are not damaged by the stresses.
摘要翻译：一种集成电路，其具有直径在约1微米至约50微米之间的导电通孔。现有技术的通孔具有不小于0.3微米至不超过0.8微米的直径。以这种方式，诸如压在集成电路的顶表面上的那些应力可以被大的通孔吸收并传递过去的脆弱层，例如低k层，使得易碎层不被应力损坏。

3. 发明授权

US6002171A Integrated heat spreader/stiffener assembly and method of assembly for semiconductor package 失效
标题翻译：集成散热器/加强件组件及半导体封装的组装方法
公开(公告)号：US6002171A
公开(公告)日：1999-12-14
申请号：US935834
申请日：1997-09-22
申请人： Kishor V. Desai , Sunil A. Patel , John P. McCormick
发明人： Kishor V. Desai , Sunil A. Patel , John P. McCormick
IPC分类号： H01L23/367 , H01L23/10 , H01L23/34
CPC分类号： H01L23/3675 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2924/01322 , H01L2924/15311
摘要： Provided is a multi-piece integrated heat spreader/stiffener assembly which is bonded to the substrate and die in a semiconductor package following electrical bonding of the die to the substrate, a packaging method using the integrated heat spreader/stiffener, and a semiconductor package incorporating the integrated heat spreader/stiffener. In a preferred embodiment, the integrated heat spreader/stiffener assembly has two pieces, both composed of a high modulus, high thermal conductivity material shaped to attach to each other and a die on the surface of a packaging substrate. A first piece of this assembly is bonded to the substrate surface adjacent to an electrically connected die and to the top surface of the die prior to the dispensation and curing of underfill material which provides the mechanical connection between the die and the substrate. With the first piece of the assembly in place, access may still be had to at least one edge of the die to dispense and cure the underfill epoxy. Once the underfill material is cured by heating, the second piece of the assembly is placed and bonded on the substrate either abutting or overlapping with the first piece. A ball grid array (BGA) process may then be used to apply solder balls to the underside of the substrate for subsequent bonding of the package to a circuit board for use.
摘要翻译：提供了一种多件式集成散热器/加强件组件，其在将模具电连接到基板上之后，将半导体封装中的基板和芯片接合，使用集成散热器/加强件的封装方法以及包含集成散热器/加强筋。在一个优选实施例中，集成的散热器/加强件组件具有两个部件，两部分由高模量，高热导率的材料构成，彼此相互连接并在封装基板的表面上形成一个模具。该组件的第一部分在与电连接的模具相邻的基板表面上粘合到模具的顶部表面，在分配和固化底部填充材料之前，其提供了管芯和基板之间的机械连接。随着组装的第一块到位，仍然可以进入模具的至少一个边缘以分配和固化底部填充环氧树脂。一旦底部填充材料通过加热固化，则组件的第二块被放置并结合到基板上，与第一块邻接或重叠。然后可以使用球栅阵列（BGA）工艺将焊球施加到衬底的下侧，用于随后将封装结合到电路板以供使用。

4. 发明授权

US06777314B2 Method of forming electrolytic contact pads including layers of copper, nickel, and gold 有权
标题翻译：形成包括铜，镍和金层的电解接触焊盘的方法
公开(公告)号：US06777314B2
公开(公告)日：2004-08-17
申请号：US10211914
申请日：2002-08-05
申请人： Kishor Desai , John P. McCormick , Maniam Alagaratnam
发明人： Kishor Desai , John P. McCormick , Maniam Alagaratnam
IPC分类号： H01L21326
CPC分类号： H05K3/062 , H01L21/2885 , H01L21/4853 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/13099 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H05K3/108 , H05K3/243 , H01L2224/05644 , H01L2924/00014 , H01L2224/05147 , H01L2224/05155
摘要： A method of forming an electrical contact on a surface of a substrate. A first layer of a first electrically conductive material is formed on the surface of the substrate, where the first layer is formed in a substantially contiguous sheet across the surface of the substrate. A non electrically conductive masking layer is applied to the first layer, where the masking layer leaves exposed first portions of the first layer and covers second portions of the first layer. The substrate is immersed in a first electrolytic plating bath, and a first electrical potential is applied between the first layer and the first electrolytic plating bath, thereby causing the formation of a second layer of a second electrically conductive material on the exposed first portions of the first layer. The substrate is immersed in a second electrolytic plating bath, and a second electrical potential is applied between the first layer and the second electrolytic plating bath, thereby causing the formation of a third layer of a third electrically conductive material on the second layer. The masking layer is removed from the substrate to expose the second portions of the first layer, and the exposed second portions of the first layer are removed to form discrete contact pads from the first portions of the first layer and the overlying second layer and third layer.
摘要翻译：在基板的表面上形成电接触的方法。在衬底的表面上形成第一导电材料第一层，其中第一层在基片的表面上形成在基本连续的片材中。将非导电掩蔽层施加到第一层，其中掩蔽层离开第一层的暴露的第一部分并覆盖第一层的第二部分。将衬底浸入第一电解电镀浴中，并且在第一层和第一电解镀浴之间施加第一电位，由此在第二层导电材料的暴露的第一部分上形成第二导电材料层第一层将衬底浸入第二电解镀浴中，并且在第一层和第二电解镀浴之间施加第二电位，从而在第二层上形成第三层第三导电材料层。从衬底去除掩模层以暴露第一层的第二部分，并且去除第一层的暴露的第二部分以从第一层的第一部分和上覆的第二层和第三层形成分立的接触焊盘。

5. 发明授权

US3939699A Tensiometer with remote sensing unit 失效
标题翻译：张力计带遥感单元
公开(公告)号：US3939699A
公开(公告)日：1976-02-24
申请号：US509900
申请日：1974-09-27
申请人： John P. McCormick
发明人： John P. McCormick
IPC分类号： G01N7/14
CPC分类号： G01N7/14
摘要： A tensiometer having a vacuum gauge which is connected to a sensing unit including a ceramic cup, which is located remote from said gauge, by a conductor in the form of a capillary tube. A second capillary bleeder tube communicates with and leads from the ceramic cup and has a second end which is located below the level of the other end of the conducting tube, so that when said second end of the bleeder tube is exposed, the escape of air therefrom can be visually determined, during purging of the device, so that after all air has been removed from the tubes, the tensiometer can be sealed. The end of the conducting tube disposed remote from the ceramic cup is connected to a lower end of a sight glass, to the upper end of which is connected the gauge, so that when air has been removed from the device and the sight glass, tubes and cup are filled with water and sealed, a vacuum will be created in the system as the moisture in the earth surrounding the cup diminishes, to register this reduced moisture condition on the gauge.
摘要翻译：具有真空计的张力计，其通过毛细管形式的导体连接到包括位于远离所述量规的陶瓷杯的感测单元。第二毛细管泄放管与陶瓷杯连通并从陶瓷杯导出，并且具有位于导电管的另一端的水平面下方的第二端，使得当泄放管的所述第二端暴露时，空气逸出可以在清洗装置期间在视觉上确定，从而在从管中取出所有空气之后，可以密封张力计。远离陶瓷杯布置的导电管的端部连接到观察窗的下端，其上端连接有量规，使得当空气从设备和观察窗中移除时，管并且杯子充满水并密封，当围绕杯子的地球中的水分减少时，将在系统中产生真空，以将该减少的湿气条件记录在计量器上。

6. 发明授权

US06558978B1 Chip-over-chip integrated circuit package 有权
标题翻译：芯片芯片集成电路封装
公开(公告)号：US06558978B1
公开(公告)日：2003-05-06
申请号：US09993466
申请日：2001-11-05
申请人： John P. McCormick
发明人： John P. McCormick
IPC分类号： H01L2144
CPC分类号： H01L25/0652 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/06135 , H01L2224/131 , H01L2224/13116 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81203 , H01L2224/81805 , H01L2224/92125 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2225/06589 , H01L2924/01322 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/18161 , H01L2924/014 , H01L2924/00
摘要： Provided is a vertically integrated (“chip-over-chip”) semiconductor package and packaging method. The invention provides higher packaging density and performance, including increased functionality, decreased signal propagation delays, improved circuit switching speed, lower thermal resistance and higher thermal dissipation measurements, relative to previous package designs. According to the invention, a semiconductor package may be composed of a flip chip (or chips) overlying one or more other flip chips, all electrically bonded to flip chip bond pads on a cavity-less semiconductor substrate. The upper and lower flips chips may be assembled in a variety of different configurations and may be thermally or electrically connected to each other. In a preferred embodiment, the flip chips, particularly the lower flip chip(s), are thinned so that the overall package height is within conventional ranges for traditional single chip packages. Packages in accordance with the invention have increased access speeds between chips and reduced total chip package footprint.
摘要翻译：提供了一种垂直集成（“片上芯片”）半导体封装和封装方法。相对于以前的封装设计，本发明提供了更高的封装密度和性能，包括增加的功能，降低的信号传播延迟，改进的电路切换速度，更低的热阻和更高的热耗散测量。根据本发明，半导体封装可以由覆盖一个或多个其它倒装芯片的倒装芯片（或芯片）组成，全部电连接到无空腔半导体衬底上的倒装芯片接合焊盘。上下翻转片可以以各种不同的构造组装，并且可以彼此热或电连接。在优选实施例中，倒装芯片，特别是下倒装芯片被减薄，使得整个封装高度在传统单芯片封装的常规范围内。根据本发明的包装增加了芯片之间的访问速度并减少了总芯片封装占地面积。

7. 发明授权

US06294840B1 Dual-thickness solder mask in integrated circuit package 有权
标题翻译：集成电路封装中的双层焊锡掩模
公开(公告)号：US06294840B1
公开(公告)日：2001-09-25
申请号：US09443036
申请日：1999-11-18
申请人： John P. McCormick
发明人： John P. McCormick
IPC分类号： H01L2348
CPC分类号： H01L24/32 , H01L21/563 , H01L24/16 , H01L24/29 , H01L2224/13099 , H01L2224/16225 , H01L2224/27013 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83051 , H01L2224/83102 , H01L2224/92125 , H01L2924/01033 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H05K3/284 , H05K3/3436 , H05K3/3452 , H01L2924/00012 , H01L2924/00
摘要： Provided is a two-step, dual-thickness solder mask material on the substrate surface. The material is preferably applied in a series of screenings: A first screening of the solder mask material in the region where the chip will be placed, and a second screening of solder mask surrounding the place on the substrate surface where the die will be placed, normally over the outside edge regions of the substrate surface. The thickness of this first screening of solder mask may be from about 10 to 20 microns, while the thickness of the second screening of solder mask is about conventional thickness for a solder mask, for example from about 30 to 40 microns.
摘要翻译：提供了一种基板表面上的两步双层焊料掩模材料。该材料优选地应用于一系列筛选：在芯片将被放置的区域中的焊料掩模材料的第一次筛选，以及围绕放置模具的基底表面上的位置的焊接掩模的第二次筛选，通常在衬底表面的外边缘区域上。该焊接掩模的第一次屏蔽的厚度可以为约10至20微米，而焊接掩模的第二次屏蔽的厚度约为焊料掩模的常规厚度，例如约30至40微米。

8. 发明授权

US5780924A Integrated circuit underfill reservoir 失效
标题翻译：集成电路底层储层
公开(公告)号：US5780924A
公开(公告)日：1998-07-14
申请号：US644000
申请日：1996-05-07
申请人： John P. McCormick
发明人： John P. McCormick
IPC分类号： H01L23/28 , H01L21/56 , H01L23/495
CPC分类号： H01L21/563 , H01L2224/16225 , H01L2224/27013 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204
摘要： A method of packaging an integrated circuit. An integrated circuit is connected to a substrate. A reservoir body is applied to the substrate, and the reservoir body and substrate define at least one reservoir and at least one flow gate. The reservoir body, substrate, and integrated circuit define a flow ring which extends at least partially around the circumference of the integrated circuit. A compound is dispensed into the reservoirs, and is flowed through the flow gates and into the flow ring, underfilling the integrated circuit.
摘要翻译：一种封装集成电路的方法。集成电路连接到基板。储存器体被施加到基板上，并且储存器本体和基板限定至少一个储存器和至少一个流动闸门。储存器本体，基板和集成电路限定了至少部分地围绕集成电路的圆周延伸的流动环。化合物被分配到储存器中，并且流过流动闸门并进入流动环，对集成电路进行灌装。

9. 发明授权

US06706622B1 Bonding pad interface 有权
标题翻译：键盘接口
公开(公告)号：US06706622B1
公开(公告)日：2004-03-16
申请号：US09949207
申请日：2001-09-07
申请人： John P. McCormick
发明人： John P. McCormick
IPC分类号： H01L2144
CPC分类号： H01L24/11 , H01L2224/05001 , H01L2224/05027 , H01L2224/0508 , H01L2224/05172 , H01L2224/05184 , H01L2224/05572 , H01L2224/13099 , H01L2924/01029 , H01L2924/01073 , H01L2924/01079 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2224/05644 , H01L2924/00014 , H01L2224/05147 , H01L2224/05155
摘要： A method for providing under bump metallization on a substrate. Trenches are formed in the substrate, and a layer of first electrically conductive material is formed over the substrate. The layer of the first electrically conductive material substantially fills the trenches and substantially covers the substrate between the trenches in a contiguous sheet. The layer of the first electrically conductive material is thinned to an end point where the layer of the first electrically conductive material is substantially reduced in thickness, but still forms the contiguous sheet between the trenches. A layer of photoresist is applied over the layer of the first electrically conductive material to define openings. A second electrically conductive material is deposited into the openings. The photoresist layer is removed, and the layer of the first electrically conductive material in the contiguous sheet between the trenches is removed to isolate the first electrically conductive material in the trenches. Because the layer of the first electrically conductive material is not completely removed in the areas between the trenches, the first electrically conductive material may be used as an electrode for the electroplate deposition of the second electrically conductive material. Thus, the under bump metallization can be produced in a more economical manner. If the layer of the first electrically conductive material were to be thinned to the point where the first electrically conductive material was only left in the trenches, then it would not be feasible to used the layer of the first electrically conductive material as an electrode, and thus it would further not be feasible to electroplate the second electrically conductive material.
摘要翻译：一种用于在衬底上提供凸块下金属化的方法。在衬底中形成沟槽，并且在衬底上形成第一导电材料层。第一导电材料的层基本上填充沟槽并基本上覆盖连续片材中沟槽之间的衬底。第一导电材料的层被薄化到第一导电材料层的厚度基本上减小的端点，但是仍然在沟槽之间形成连续的片材。在第一导电材料的层上施加一层光致抗蚀剂以限定开口。第二导电材料沉积到开口中。去除光致抗蚀剂层，并且移除在沟槽之间的邻接片材中的第一导电材料层，以隔离沟槽中的第一导电材料。因为第一导电材料的层在沟槽之间的区域中没有被完全去除，所以第一导电材料可以用作电极沉积第二导电材料的电极。因此，能够以更经济的方式制造凸块下金属化。如果将第一导电材料的层变薄到第一导电材料仅留在沟槽中的点，则将第一导电材料层用作电极是不可行的，以及因此电镀第二导电材料将不可行。

10. 发明授权

US6166434A Die clip assembly for semiconductor package 失效
标题翻译：用于半导体封装的芯片组件
公开(公告)号：US6166434A
公开(公告)日：2000-12-26
申请号：US935583
申请日：1997-09-23
申请人： Kishor V. Desai , Sunil A. Patel , John P. McCormick
发明人： Kishor V. Desai , Sunil A. Patel , John P. McCormick
IPC分类号： H01L21/56 , H01L23/04 , H01L23/12
CPC分类号： H01L21/563 , H01L23/04 , H01L24/29 , H01L24/32 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/81191 , H01L2224/83102 , H01L2224/92125 , H01L2924/00014 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/01322 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/00 , H01L2924/3512 , H01L2224/0401
摘要： Provided is a die clip for use in semiconductor flip chip packaging as a replacement for the conventional combination of a heat spreader and stiffener, a packaging method using the die clip, and a semiconductor package incorporating the die clip. In a preferred embodiment, the die clip is a piece of high modulus, high thermal conductivity material shaped to attach over a die on the surface of a packaging substrate. The die clip closely engages the die while leaving some space open around the perimeter to provide access to the die. An underfill material may then be dispensed into the gap between the die and the substrate through an opening in the die clip. The underfill material is then cured, the die clip providing a heat sink and keeping the die and substrate flat and immobile during and after the curing process. A BGA process may then be used to apply solder balls to the underside of the substrate for subsequent bonding of the package to a circuit board for use.
摘要翻译：提供了一种用于半导体倒装芯片封装的芯片夹，作为热扩散器和加强件的常规组合的替代品，使用该芯片夹的封装方法以及并入该夹具的半导体封装。在一个优选实施例中，模夹是一片高模量，高导热性的材料，其被成形为附着在包装基底的表面上的模具上。模夹紧密地接合模具，同时在周边周围留出一些空间以提供对模具的接近。然后可以通过模夹中的开口将底部填充材料分配到模具和基板之间的间隙中。然后固化底部填充材料，模具夹提供散热器并且在固化过程中和之后使模具和基底保持平坦且不变。然后可以使用BGA工艺将焊球施加到衬底的下侧，以便随后将封装连接到电路板以供使用。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式