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1. 发明专利

JP2014044194A Magnetism detection circuit using magnetism detection element 有权
标题翻译：使用MAGNETISM检测元件的磁性检测电路
公开(公告)号：JP2014044194A
公开(公告)日：2014-03-13
申请号：JP2013035838
申请日：2013-02-26
申请人： Toyota Central R&D Labs Inc , 株式会社豊田中央研究所 , Denso Corp , 株式会社デンソー
发明人： HOSOKAWA HIDEKI , OTA NORIKAZU , TSURUHARA TAKAO , HARADA TOMOYUKI
IPC分类号： G01R33/07
摘要： PROBLEM TO BE SOLVED: To solve a problem in a conventional removal technique that it is necessary to eliminate influence of an offset voltage contained in an element in a four terminal type magnetism detection element where, when a current is fed between a first terminal and a third terminal, a voltage proportional to a magnetic flux density is output between a second terminal and a fourth terminal, and a current is fed between the third terminal and the first terminal, a voltage proportional to a magnetic flux density is output between a third terminal and a first terminal, and delay may occur in the signal processing.SOLUTION: The third terminal and fourth terminal having a same polarity of an offset voltage while having different voltages proportional to the magnetic flux density are alternately connected with a first input of a differential amplifier. Similarly the first terminal and second terminal having a same polarity of an offset voltage while having different voltages proportional to the magnetic flux density are alternately connected with a second input of the differential amplifier. The offset voltage is of a DC component, thereby failing to affect the amplified voltage.
摘要翻译：要解决的问题：为了解决现有的去除技术中的问题，需要消除包含在四端型磁检测元件中的元件中的偏移电压的影响，其中当在第一端子和第二端子之间馈送电流时，第三端子，在第二端子和第四端子之间输出与磁通密度成比例的电压，并且在第三端子和第一端子之间馈送电流，在第三端子与第三端子之间输出与磁通密度成正比的电压和第一端子，并且在信号处理中可能发生延迟。解决方案：具有与磁通密度成比例的不同电压的偏移电压具有相同极性的第三端子和第四端子与差分的第一输入端交替连接放大器。类似地，具有与磁通密度成比例的不同电压的偏移电压具有相同极性的第一端子和第二端子与差分放大器的第二输入交替连接。偏移电压为直流分量，不能影响放大电压。

2. 发明专利

JP2011196904A Sensor voltage processing circuit 有权
标题翻译：传感器电压处理电路
公开(公告)号：JP2011196904A
公开(公告)日：2011-10-06
申请号：JP2010065709
申请日：2010-03-23
申请人： Denso Corp , Toyota Central R&D Labs Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： HOSOKAWA HIDEKI , OTA NORIKAZU , SUZUKI MASATO
IPC分类号： G01D5/244
摘要： PROBLEM TO BE SOLVED: To quickly adjust an offset voltage and a gain of a sensor voltage processing circuit.SOLUTION: The sensor voltage processing circuit 100 includes: an amplifier circuit 120 which outputs a voltage obtained by amplifying a sensor voltage based on the offset voltage, and adjusts the offset voltage and the gain; an extremal value storage circuit 160 for storing an extremal value of an output voltage of the amplifier circuit 120; a binarization circuit 200 for binarizing the output voltage of the amplifier circuit based on the extremal value stored in the extremal value storage circuit; and an adjusting circuit 400. During the initializing processing, the adjusting circuit 400, (1) sets the gain at a maximum value, (2) adjusts the offset voltage so that the output voltage of the amplifier circuit enters the intermediate zone of the operating voltage range of the amplifier circuit, (3) adapts the extremal value to a voltage within the intermediate zone, (4) reduces the gain and corrects the extremal value when a variation width from the extremal value of the output voltage of the amplifier circuit exceeds a given width, and (5) repeats the processing (4) until the output voltage of the amplifier circuit indicates a variation pattern specific to the rotation movement of a rotating body.
摘要翻译：要解决的问题：快速调整传感器电压处理电路的失调电压和增益。解决方案：传感器电压处理电路100包括：放大器电路120，其输出通过基于偏移电压放大传感器电压而获得的电压，并调整偏移电压和增益; 用于存储放大器电路120的输出电压的极值的极值存储电路160; 二值化电路200，用于基于存储在极值存储电路中的极值来二值化放大器电路的输出电压; 以及调整电路400.在初始化处理期间，调整电路400（1）将增益设定为最大值，（2）调整偏移电压，使得放大器电路的输出电压进入操作的中间区域放大器电路的电压范围，（3）将极值适应于中间区域内的电压，（4）当放大器电路的输出电压的极值的变化幅度超过时，降低增益并修正极值给定的宽度，和（5）重复处理（4），直到放大器电路的输出电压指示与旋转体的旋转运动相关的变化模式。

3. 发明专利

JP2011153904A Sensor-voltage processing circuit 有权
标题翻译：传感器电压处理电路
公开(公告)号：JP2011153904A
公开(公告)日：2011-08-11
申请号：JP2010015412
申请日：2010-01-27
申请人： Denso Corp , Toyota Central R&D Labs Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： MIZUNO KENTARO , HASHIMOTO SHOJI , OTA NORIKAZU , TAKEUCHI HISAYUKI , OKAMURA AKIRA , ITO OSAMU
IPC分类号： G01R19/04 , G01L9/04
摘要： PROBLEM TO BE SOLVED: To provide a sensor-voltage processing circuit, capable of properly removing a true signal voltage, in opposition to the fluctuations of a supply voltage. SOLUTION: A piezoresistive element 23 of a combustion pressure sensor 20 is connected to a power source via a constant-current source 22. In the sensor voltage processing circuit 30, a grounded first capacitor 32 and a second capacitor 33, connected to the power source via a constant-voltage source 34, are connected through voltage preservation wiring 37. The capacity ratio between the first capacitor 32 and the second capacitor 33 is set so as to agree with the ratio between a reference preservation voltage which is substantially an intermediate value of an estimated fluctuation range of a preservation voltage Vk and a voltage, determined by subtracting the reference preservation voltage from the rated voltage of the power source. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种与电源电压的波动相反的能够适当地去除真实信号电压的传感器电压处理电路。解决方案：燃烧压力传感器20的压阻元件23通过恒流源22连接到电源。在传感器电压处理电路30中，接地的第一电容器32和第二电容器33连接到经由恒压源34的电源通过电压保持布线37连接。第一电容器32和第二电容器33之间的容量比被设定为与基本保持电压基本上为保存电压Vk的推定波动范围的中间值和通过从电源的额定电压减去基准保持电压而决定的电压。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2011141179A Voltage processing circuit 有权
标题翻译：电压加工电路
公开(公告)号：JP2011141179A
公开(公告)日：2011-07-21
申请号：JP2010001668
申请日：2010-01-07
申请人： Denso Corp , Toyota Central R&D Labs Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： OTA NORIKAZU , HOSOKAWA HIDEKI , SUZUKI MASATO
IPC分类号： G01D5/244
摘要： PROBLEM TO BE SOLVED: To provide a circuit for outputting a timing signal to be inverted at timing accurately corresponding to a change of a rotation angle of a rotating body.
SOLUTION: A voltage processing circuit includes an amplification circuit 110 amplifying a signal voltage inputted from a sensor 10; a peak hold circuit 120 holding a peak value Vp of an amplified voltage; a bottom hold circuit 130 holding a bottom value Vb of the amplified voltage; a threshold voltage output circuit 140 outputting a voltage dividing ratio A which assumes a higher value as a difference ΔV between the peak value Vp and the bottom value Vb is decreased, and a threshold voltage Vref calculated according to the formula of Vref=Vb+A×(Vp-Vb); and a circuit 150 outputting the timing signal to be inverted when the amplified voltage is changed beyond the threshold voltage Vref. A change of a signal waveform by the difference ΔV between the peak value Vp and the bottom value Vb can be compensated, allowing the acquirement of the timing signal to be inverted at the timing accurately corresponding to the change of the rotation angle.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种电路，用于以与旋转体的旋转角度的变化精确对应的定时输出要反转的定时信号。解决方案：电压处理电路包括放大电路110，放大从传感器10输入的信号电压; 保持放大电压的峰值Vp的峰值保持电路120; 保持放大电压的底值Vb的底部保持电路130; 将阈值电压输出电路140输出作为峰值Vp和底值Vb之间的差ΔV的较高值的分压比A减小，并且根据Vref = Vb + A的公式计算出的阈值电压Vref ×（VP-VB）; 以及当放大的电压变化超过阈值电压Vref时，输出要反相的定时信号的电路150。可以补偿信号波形与峰值Vp和底部值Vb之差ΔV的变化，从而能够以与旋转角度的变化精确对应的时刻反转定时信号。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2011135225A Signal processing circuit 有权
标题翻译：信号处理电路
公开(公告)号：JP2011135225A
公开(公告)日：2011-07-07
申请号：JP2009291387
申请日：2009-12-22
申请人： Denso Corp , Toyota Central R&D Labs Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： OTA NORIKAZU , MIZUNO KENTARO , KUWABARA MAKOTO , AZEYANAGI SUSUMU
IPC分类号： H03F3/38 , H03F3/34
摘要： PROBLEM TO BE SOLVED: To provide a processing circuit which removes the influence of an offset voltage (having periodically reversing polarities) contained in the output voltage of a chopper amplifier better therefrom. SOLUTION: A signal processing circuit is equipped with: a first sampling and holding circuit 110 which performs a sampling and holding operation for an output voltage from a chopper amplifier 500 at a predetermined period; an adder circuit 120 which adds the output voltage from a chopper amplifier to an output voltage from the first sampling and holding circuit; and a second sampling and holding circuit 130 which performs a sampling and holding operation for an output voltage from an adder circuit at a predetermined period. Between a first timing of reversing an offset voltage superimposed on the output voltage from a chopper amplifier and a second timing of performing the sampling and holding operation in the first sampling and holding circuit, a third timing of performing the sampling and holding operation in the second sampling and holding circuit is set. A voltage with the offset voltages of reverse polarities being offset is outputted from the second sampling and holding circuit 130. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种处理电路，其更好地消除包含在斩波放大器的输出电压中的偏移电压（具有周期性反转极性）的影响。信号处理电路配备有：第一采样保持电路110，其以预定周期对来自斩波放大器500的输出电压进行采样和保持操作; 加法器电路120，其将来自斩波放大器的输出电压与来自第一采样保持电路的输出电压相加; 以及第二采样保持电路130，其以预定周期对来自加法器电路的输出电压进行采样和保持操作。在反转来自斩波放大器的输出电压上叠加的偏移电压的第一定时与在第一采样保持电路中执行采样和保持操作的第二定时之间，在第二定时中执行第二采样保持操作采样保持电路设置。从第二采样保持电路130输出具有偏移的反极性偏移电压的电压。（C）2011，JPO和INPIT

6. 发明专利

JP2011009938A Hold circuit 有权
标题翻译：保持电路
公开(公告)号：JP2011009938A
公开(公告)日：2011-01-13
申请号：JP2009149981
申请日：2009-06-24
申请人： Denso Corp , Toyota Central R&D Labs Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： MIZUNO KENTARO , HASHIMOTO SHOJI , OTA NORIKAZU , TAKEUCHI HISAYUKI , ITO OSAMU
IPC分类号： H03K17/687 , G11C27/02
摘要： PROBLEM TO BE SOLVED: To provide a hold circuit for suppressing fluctuation in output voltage during hold operation.SOLUTION: The hold circuit 100 includes a hold capacitor 140, an operational amplifier 110, a first pMOS 130, a buffer amplifier 150, and a voltage adjustment circuit 120. The voltage of an input signal is applied to a non-inverted input end of the operational amplifier 110, and the voltage of the hold capacitor 140 is applied to an inverted input end. The first pMOS 130 with a gate G and a drain D connected thereto functions as a rectifying device for allowing a current to flow to the drain D from a source S. An input end of the rectifying device is connected to an output end of the operational amplifier, and the output end thereof is connected to the other end of the hold capacitor. The voltage adjustment circuit 120 is connected between the output end of the operation amplifier and the input end of rectifying device, and when the voltage of the output end of the operational amplifier is lower than the voltage of the output end of the buffer amplifier, the voltage of the input end of the rectifying device is made higher than the voltage of the output end of the operational amplifier.
摘要翻译：要解决的问题：提供一种用于抑制保持操作期间输出电压波动的保持电路。解决方案：保持电路100包括保持电容器140，运算放大器110，第一pMOS 130，缓冲放大器150和电压输入信号的电压被施加到运算放大器110的非反相输入端，并且保持电容器140的电压被施加到反相输入端。连接有栅极G和漏极D的第一个pMOS 130用作用于允许电流从源极S流到漏极D的整流装置。整流装置的输入端连接到操作的输出端放大器，其输出端连接到保持电容的另一端。电压调节电路120连接在运算放大器的输出端和整流装置的输入端之间，并且当运算放大器的输出端的电压低于缓冲放大器的输出端的电压时，使整流装置的输入端的电压高于运算放大器的输出端的电压。

7. 发明专利

JP2010085328A Hold circuit 有权
标题翻译：保持电路
公开(公告)号：JP2010085328A
公开(公告)日：2010-04-15
申请号：JP2008256713
申请日：2008-10-01
申请人： Denso Corp , Toyota Central R&D Labs Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： MIZUNO KENTARO , OTA NORIKAZU , OHIRA YOSHIE , MAKINO YASUAKI , ARIYOSHI HIROMI , NAGASE KAZUYOSHI
IPC分类号： G01R19/04 , H01L21/822 , H01L27/04
CPC分类号： G11C27/02
摘要： PROBLEM TO BE SOLVED: To provide a hold circuit holding a peak voltage or a bottom voltage of input voltages varying with time. SOLUTION: The hold circuit 10 includes an input terminal 20 inputting a voltage, an output terminal 22 outputting a held voltage, a reference voltage terminal 24 connecting to a ground voltage, an operational amplifier 30, a switch circuit 32, a capacitor 36, and an impedance converting circuit 38. In the switch circuit 32, one main electrode 34b and a gate electrode 34d are connected to a connection point 26, another main electrode 34a is equipped with an insulated gate type transistor 34 connected to an output terminal 30c of the operational amplifier 30, and a semiconductor well region of the insulated gate type transistor 34 is connected to the output terminal 22 through a bias electrode 34c. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供保持输入电压随时间变化的峰值电压或底部电压的保持电路。解决方案：保持电路10包括输入电压的输入端子20，输出保持电压的输出端子22，连接到接地电压的参考电压端子24，运算放大器30，开关电路32，电容器 36和阻抗转换电路38.在开关电路32中，一个主电极34b和栅电极34d连接到连接点26，另一个主电极34a配备有连接到输出端子的绝缘栅型晶体管34 30c以及绝缘栅型晶体管34的半导体阱区域通过偏置电极34c与输出端子22连接。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2010078358A Binarization circuit and phase difference discriminator 有权
标题翻译：双向电路和相位差分解码器
公开(公告)号：JP2010078358A
公开(公告)日：2010-04-08
申请号：JP2008244369
申请日：2008-09-24
申请人： Denso Corp , Toyota Central R&D Labs Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： OTA NORIKAZU , HOSOKAWA HIDEKI , OBA NOBUKAZU , NAKATANI MASAMICHI , OKADA HIROSHI
IPC分类号： G01R19/25 , H03K5/08 , H03K5/26
摘要： PROBLEM TO BE SOLVED: To provide a binarization circuit which binarizes an input voltage. SOLUTION: The binarization circuit 10 includes: an input terminal 20; a first output terminal 26; a second output terminal 28; a peak hold circuit 30; a bottom hold circuit 40; a threshold calculation circuit 50; a first comparison circuit 60; a second comparison circuit 70; a first selection circuit 80; a second selection circuit 90; a third selection circuit 100; and a fourth selection circuit 110. The first selection circuit 80 outputs a binarized signal, while the second selection circuit 90 outputs a delayed binarized signal. The peak hold circuit 30 decreases a peak voltage on the basis of the delayed binarized signal, while the bottom hold circuit 40 increases a bottom voltage on the basis of the delayed binarized signal. The delayed binarized signal is thereby surely delayed with respect to the binarized signal. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供二值化输入电压的二值化电路。二值化电路10包括：输入端子20; 第一输出端子26; 第二输出端子28; 峰值保持电路30; 底部保持电路40; 阈值计算电路50; 第一比较电路60; 第二比较电路70; 第一选择电路80; 一个第二选择电路90; 第三选择电路100; 和第四选择电路110.第二选择电路80输出二值化信号，而第二选择电路90输出延迟二值化信号。峰值保持电路30基于延迟二值化信号降低峰值电压，而底部保持电路40基于延迟二值化信号增加底部电压。因此，延迟二值化信号相对于二值化信号可靠地延迟。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2010028215A Hold circuit 有权
标题翻译：保持电路
公开(公告)号：JP2010028215A
公开(公告)日：2010-02-04
申请号：JP2008183989
申请日：2008-07-15
申请人： Denso Corp , Toyota Central R&D Labs Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： HOSOKAWA HIDEKI , MIZUNO KENTARO , OTA NORIKAZU , OHIRA YOSHIE , ARIYOSHI HIROMI , MAKINO YASUAKI , NAGASE KAZUYOSHI
IPC分类号： H03K5/1532
摘要： PROBLEM TO BE SOLVED: To provide a hold circuit capable of reducing power consumption.
SOLUTION: The peak hold circuit 2 comprises a switch circuit 4 formed between one electrode of a capacitor 10 for holding a signal and an input terminals 20. The switch circuit 4 comprises an insulated gate transistor 5, and a gate electrode 5c is connected to a switching circuit 15. The insulated gate transistor 5 is controlled by the switching circuit 15, and the insulated gate transistor 5 is shut down when the peak voltage of an output voltage Vout is held. The peak voltage of the output voltage Vout is held without a change in electron charge stored in the capacitor 10. In addition, the switching circuit 15 is connected to a resetting terminal 19. When the output voltage Vout is reset, the insulated gate transistor 5 is shut down. Current does not flow from the input terminal 20 to GND, so that power consumption is suppressed.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供能够降低功耗的保持电路。解决方案：峰值保持电路2包括形成在用于保持信号的电容器10的一个电极和输入端子20之间的开关电路4.开关电路4包括绝缘栅极晶体管5，栅极电极5c 连接到开关电路15.绝缘栅晶体管5由开关电路15控制，并且当保持输出电压Vout的峰值电压时，绝缘栅晶体管5截止。保持输出电压Vout的峰值电压而不会在电容器10中存储电子电荷的变化。此外，开关电路15连接到复位端子19.当输出电压Vout被复位时，绝缘栅极晶体管5 被关闭电流不从输入端子20流向GND，从而抑制功耗。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2009010827A Noise removing circuit and comparator circuit equipped with the same 有权
标题翻译：噪声消除电路和与此相同的比较器电路
公开(公告)号：JP2009010827A
公开(公告)日：2009-01-15
申请号：JP2007171710
申请日：2007-06-29
申请人： Denso Corp , Toyota Central R&D Labs Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： OTA NORIKAZU , HOSOKAWA HIDEKI , NAKATANI MASAMICHI , OBA NOBUKAZU
IPC分类号： H03K5/1252 , H03H11/04
CPC分类号： H03K5/1252 , H03K5/086
摘要： PROBLEM TO BE SOLVED: To surely remove signal changes, caused by noise components, from the comparison signals of a comparator. SOLUTION: A comparator circuit is equipped with the comparator 20 and a timer circuit 30. The timer circuit 30 outputs output signal V OUT , while inverting it between low level and high level, when the high level is maintained at least over from a first timing and a second timing, after the comparison signal V COMP of the comparator 20 is inverted from low level to high level and is output. The timer circuit 30 has a memory means 38 for storing the fact that the comparison signal V COMP has been inverted from low level to high level with the first timing, when this is confirmed the fact. The memory means 38 cancels the memory state, when the comparison signal V COMP is inverted between the first timing and the second timing. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：从比较器的比较信号中可靠地消除由噪声分量引起的信号变化。
解决方案：比较器电路配备有比较器20和定时器电路30.定时器电路30输出输出信号V OUT ，同时在低电平和高电平之间反相，当高电平在比较器20的比较信号V SB = COMP 从低电平反相到高电平之后，从第一定时和第二定时至少保持电平，并输出。定时器电路30具有存储装置38，用于存储由第一定时将比较信号V SB> COMP 从低电平转换为高电平的事实，这确认了事实。当第一定时和第二定时之间的比较信号V SB = COMP 反转时，存储装置38取消存储状态。版权所有（C）2009，JPO＆INPIT

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