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1. 发明授权

US5438299A Phase-locked loop circuit 失效
标题翻译：锁相环电路
公开(公告)号：US5438299A
公开(公告)日：1995-08-01
申请号：US220057
申请日：1994-03-30
申请人： Toshizi Shimada , Yasunori Kanai , Yoshio Watanabe
发明人： Toshizi Shimada , Yasunori Kanai , Yoshio Watanabe
IPC分类号： H03L7/093 , H03L7/089 , H03L7/099 , H03L7/107 , H03L7/08 , H03L7/085
CPC分类号： H03L7/0891 , H03L7/099 , H03L2207/06
摘要： A PLL circuit comprising a phase comparator unit which forms a differentiation signal based upon both edges of an external signal, outputs an early pulse only during a period in which the differentiation signal is overlapped on a period from the leading edge to the trailing edge of a reference signal, and outputs a late pulse only during a period in which the differentiation signal is overlapped on a period from the trailing edge to the leading edge thereof, a charge pump unit which calculates and compares the amounts of integration of the early pulse and the late pulse, lowers the output voltage when the amount of the late pulse is larger than the amount of the early pulse and raises the output voltage when it is smaller, and a VCO which outputs a corrected reference signal of which the frequency decreases or increases accompanying the increase or decrease in the output voltage of the charge pump unit, wherein the VCO is controlled by the output voltage of the charge pump unit and by the early pulse and the late pulse, and works to raise the oscillation frequency when the late pulse is longer than the early pulse and to lower the oscillation frequency when it is shorter.
摘要翻译：一种PLL电路，包括相位比较器单元，该相位比较器单元基于外部信号的两个边缘形成微分信号，仅在从差分信号重叠的周期期间输出早期脉冲，该周期在从前沿到后沿的周期参考信号，并且仅在从后沿到其前沿的周期中的差分信号重叠的时段期间输出延迟脉冲;电荷泵单元，其计算并比较早期脉冲和延迟脉冲，当后期脉冲的量大于早期脉冲的量时降低输出电压，并且当其较小时升高输出电压，以及输出频率随之减少或增加的校正参考信号的VCO 电荷泵单元的输出电压的增加或减小，其中VCO由电荷泵单元的输出电压和早期脉冲和晚期脉冲，并且当延迟脉冲比早期脉冲长时，提高振荡频率，并且当其较短时降低振荡频率。

2. 发明授权

US5382923A Charge-pump circuit for use in phase locked loop 失效
标题翻译：用于锁相环的电荷泵电路
公开(公告)号：US5382923A
公开(公告)日：1995-01-17
申请号：US223320
申请日：1994-04-05
申请人： Toshizi Shimada , Yasunori Kanai , Yoshio Watanabe
发明人： Toshizi Shimada , Yasunori Kanai , Yoshio Watanabe
IPC分类号： H03K17/06 , H03L7/089 , H03L7/093
CPC分类号： H03L7/0895
摘要： A charge-pump circuit for controlling a voltage controlled oscillator by converting a phase difference between two input signals, which never become low at the same time, into a voltage. The charge-pump circuit includes first and second feeder circuits, made of bipolar transistors, outputting current in accordance with the input signals; a capacitor circuit having first, second, and third capacitors, and the first and the second or the first and the third capacitors are charged by the output current from the first or the second feeder circuit; and a differential amplifying circuit amplifying the voltage between the ends of the first capacitor to a predetermined voltage for output. The differential amplifying circuit operates to draw the same leakage current from the second and the third capacitors when the first capacitor is not being charged. The charge-pump circuit is effectively used to control the frequency of the voltage controlled oscillator in an PLL circuit having a phase comparator, a voltage controlled oscillator, and an output circuit.
摘要翻译：一种电荷泵电路，用于通过将两个不会同时变低的输入信号之间的相位差转换为电压来控制压控振荡器。电荷泵电路包括由双极晶体管制成的第一和第二馈电电路，根据输入信号输出电流; 具有第一，第二和第三电容器的电容器电路，并且第一和第二或第一和第三电容器由来自第一或第二馈电电路的输出电流充电; 以及差分放大电路，将第一电容器的端部之间的电压放大到预定电压以输出。当第一电容器未被充电时，差分放大电路用于从第二和第三电容器抽出相同的漏电流。电荷泵电路有效地用于控制具有相位比较器，压控振荡器和输出电路的PLL电路中的压控振荡器的频率。

3. 发明授权

US5327021A Waveform synthesizing circuit 失效
标题翻译：波形合成电路
公开(公告)号：US5327021A
公开(公告)日：1994-07-05
申请号：US895901
申请日：1992-06-09
申请人： Yasunori Kanai , Toshizi Shimada , Takahiko Nakao , Yoshio Watanabe
发明人： Yasunori Kanai , Toshizi Shimada , Takahiko Nakao , Yoshio Watanabe
IPC分类号： H03K17/16 , H03K17/60 , H04L12/413 , H04L25/02 , H04L25/03 , H03K5/24
CPC分类号： H04L25/0286 , H03K17/16 , H03K17/603 , H04L12/40039 , H04L12/413 , H04L25/03834 , H04L25/0272
摘要： A waveform synthesizing circuit comprises a plurality of signal output switching means for outputting predetermined magnitudes of voltage or current signals when a voltage or current value of an input pulse reaches preliminarily assigned comparing reference values, a signal summing means for superimposing output signals from a plurality of signal output switching means for summing, and a comparing signal switching means detecting the rising and falling of the input pulse, providing the comparing reference values with given differences between a plurality of signal output switching means according to an order of operation of a plurality of signal output switching means upon the detection of a rise, and providing the comparing reference values, which are different from those for rising, with given differences between a plurality of signal output switching means according to an order of operation of a plurality of signal output switching means upon the detection of a fall.
摘要翻译：一种波形合成电路包括多个信号输出切换装置，用于当输入脉冲的电压或电流值达到预先分配的比较参考值时输出预定幅度的电压或电流信号;信号求和装置，用于叠加来自多个和用于求和的信号输出切换装置，以及检测输入脉冲的上升和下降的比较信号切换装置，根据多个信号的操作顺序，提供比较参考值与多个信号输出切换装置之间的给定差异输出切换装置，根据多个信号输出切换装置的操作顺序，给出多个信号输出切换装置之间的给定差异，提供与上升相比不同的比较基准值在检测到秋天。

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