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    • 1. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US07385863B2
    • 2008-06-10
    • US11716710
    • 2007-03-12
    • Toshiyuki NishiharaYoshio Sakai
    • Toshiyuki NishiharaYoshio Sakai
    • G11C7/00G11C8/00H03K19/003
    • G11C29/4401G11C29/44G11C29/846G11C2029/1208
    • A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein defective memory addresses in regions are stored in a second memory array. When a memory address for accessing the first memory array is input, the defective memory address of the memory region including the memory to be accessed is read out from the second memory array. In this way, the addresses of defective memory in 16 word lines worth of a memory region are stored in the second memory array 2, therefore addresses of a wider range of defective memory can be stored. For this reason, it becomes possible to repair defects occurring at random efficiently.
    • 一种半导体存储器件,其能够通过使用有限的冗余存储器来有效地修复缺陷,同时抑制伴随着存储器缺陷的修复的存取速度的下降,其中第一存储器阵列被分成用于每16个字线的多个存储区域, 其中区域中的有缺陷的存储器地址存储在第二存储器阵列中。 当输入用于访问第一存储器阵列的存储器地址时,从第二存储器阵列读出包括要访问的存储器的存储器区域的缺陷存储器地址。 以这种方式,存储在存储器区域中的16个字线的缺陷存储器的地址被存储在第二存储器阵列2中,因此可以存储较宽范围的有缺陷的存储器的地址。 为此,可以有效地修复随机发生的缺陷。
    • 4. 发明申请
    • Semiconductor memory device
    • 半导体存储器件
    • US20050128830A1
    • 2005-06-16
    • US11000048
    • 2004-12-01
    • Toshiyuki NishiharaYoshio Sakai
    • Toshiyuki NishiharaYoshio Sakai
    • G11C29/04G11C7/00G11C8/00G11C8/06G11C29/00G11C29/44
    • G11C29/4401G11C29/44G11C29/846G11C2029/1208
    • A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein defective memory addresses in regions are stored in a second memory array. When a memory address for accessing the first memory array is input, the defective memory address of the memory region including the memory to be accessed is read out from the second memory array. In this way, the addresses of defective memory in 16 word lines worth of a memory region are stored in the second memory array 2, therefore addresses of a wider range of defective memory can be stored. For this reason, it becomes possible to repair defects occurring at random efficiently.
    • 一种半导体存储器件,其能够通过使用有限的冗余存储器来有效地修复缺陷,同时抑制伴随着存储器的缺陷的修复的存取速度的下降,其中第一存储器阵列被分成用于每16个字线的多个存储区域, 其中区域中的有缺陷的存储器地址存储在第二存储器阵列中。 当输入用于访问第一存储器阵列的存储器地址时,从第二存储器阵列读出包括要访问的存储器的存储器区域的缺陷存储器地址。 以这种方式,存储在存储器区域中的16个字线的缺陷存储器的地址被存储在第二存储器阵列2中,因此可以存储较宽范围的有缺陷的存储器的地址。 为此,可以有效地修复随机发生的缺陷。
    • 6. 发明申请
    • Semiconductor memory device
    • 半导体存储器件
    • US20070165468A1
    • 2007-07-19
    • US11716710
    • 2007-03-12
    • Toshiyuki NishiharaYoshio Sakai
    • Toshiyuki NishiharaYoshio Sakai
    • G11C29/00G11C7/00
    • G11C29/4401G11C29/44G11C29/846G11C2029/1208
    • A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein defective memory addresses in regions are stored in a second memory array. When a memory address for accessing the first memory array is input, the defective memory address of the memory region including the memory to be accessed is read out from the second memory array. In this way, the addresses of defective memory in 16 word lines worth of a memory region are stored in the second memory array 2, therefore addresses of a wider range of defective memory can be stored. For this reason, it becomes possible to repair defects occurring at random efficiently.
    • 一种半导体存储器件,其能够通过使用有限的冗余存储器来有效地修复缺陷,同时抑制伴随着存储器的缺陷的修复的存取速度的下降,其中第一存储器阵列被分成用于每16个字线的多个存储区域, 其中区域中的有缺陷的存储器地址存储在第二存储器阵列中。 当输入用于访问第一存储器阵列的存储器地址时,从第二存储器阵列读出包括要访问的存储器的存储器区域的缺陷存储器地址。 以这种方式,存储在存储器区域中的16个字线的缺陷存储器的地址被存储在第二存储器阵列2中,因此可以存储更宽范围的有缺陷的存储器的地址。 为此,可以有效地修复随机发生的缺陷。
    • 7. 发明授权
    • Passive optical network system and method of data transmission in the passive optical network
    • 无源光网络中的无源光网络系统和数据传输方法
    • US07920791B2
    • 2011-04-05
    • US12073037
    • 2008-02-28
    • Yoshio SakaiKazuyuki Mori
    • Yoshio SakaiKazuyuki Mori
    • H04J14/00
    • H04L1/0041H04B10/272H04L1/0063H04L1/0078H04Q11/0067H04Q2011/0086
    • Regarding the passive optical network (PON) system of the present invention, in an OLT, data of different bit rates is framed, and framed data rows are subjected to FEC encoding processing without changing the line up of the data, and a check bit is added to the end of the frame, and an optical signal that has been modulated in accordance with the data row to which the check bit has been added is transmitted to the optical transmission line. Then in an ONU that corresponds to a high speed bit rate to which an optical signal from the OLT has been applied via a power splitter, forward error correction of the reception data is performed. As a result in a PON system in which data of different bit rates coexist, the minimum reception rate of a high speed ONU can be improved without having an influence on a low speed ONU.
    • 关于本发明的无源光网络(PON)系统,在OLT中,不同比特率的数据被成帧,并且成帧的数据行经受FEC编码处理而不改变数据的排队,并且校验位 加到帧的结尾,并且已经根据添加有校验位的数据行调制的光信号被发送到光传输线。 然后,在对应于通过功率分配器施加了来自OLT的光信号的高速比特率的ONU中,执行接收数据的前向纠错。 结果,在不同比特率的数据共存的PON系统中,可以提高高速ONU的最小接收速率,而不会对低速ONU产生影响。
    • 9. 发明授权
    • Linear measurement apparatus
    • 线性测量装置
    • US07684057B2
    • 2010-03-23
    • US11802065
    • 2007-05-18
    • Yoshio Sakai
    • Yoshio Sakai
    • G01B11/14
    • G01B11/022A61B5/1072A61B5/1075A61B5/1079
    • A linear measurement apparatus includes a measuring unit including at least one first noncontact distance measuring sensor and one second noncontact distance measuring sensor supported at a frame and aligned on opposite sides of a measured object. The measuring unit measures a plurality of first gap distances to a plurality of first object positions in a plurality of parallel first measurement lines and a plurality of second gap distances to a plurality of second object positions in a plurality of parallel second measurement lines. A distance calculator calculates a plurality of candidate object lengths on the basis of the first and second gap distances, each candidate object length being a distance between one of the first object positions and one of the second object positions. A maximum selector selects a maximum object length from among the plurality of candidate object lengths.
    • 线性测量装置包括测量单元,该测量单元包括至少一个第一非接触式距离测量传感器和一个支撑在框架处并对准测量对象的相对侧的第二非接触距离测量传感器。 测量单元测量多个平行的第一测量线中的多个第一对象位置和多个平行的第二测量线中的多个第二对象位置的多个第二间隙距离的多个第一间隙距离。 距离计算器基于第一和第二间隙距离计算多个候选对象长度,每个候选对象长度是第一对象位置中的一个与第二对象位置之一之间的距离。 最大选择器从多个候选对象长度中选择最大对象长度。
    • 10. 发明申请
    • Optical transmission device, scrambling method, and descrambling method
    • 光传输设备,扰频方式和解扰方式
    • US20080253568A1
    • 2008-10-16
    • US12081220
    • 2008-04-11
    • Yoshio SakaiKazuyuki Mori
    • Yoshio SakaiKazuyuki Mori
    • H04J14/00H04K1/00
    • H04J3/1694H04J3/1658H04Q11/0067H04Q2011/0086
    • A first header-attaching unit attaches to data of a low speed bit rate A, a header of the bit rate A. A second header-attaching unit attaches the header of the bit rate A to data of a high speed bit rate B. A combining unit combines outputs of the first and the second header-attaching units. A low speed scrambling unit performs a scrambling process on combined data by using a clock corresponding to the bit rate A. A high speed scrambling unit performs a scrambling process on the data of the bit rate B by using a clock corresponding to the bit rate B. During a timing corresponding to the bit rate A in the frame, a selector selects an output of the low speed scrambling unit. During a timing corresponding to the bit rate B in the frame, the selector selects an output of the high speed scrambling unit.
    • 第一标题附加单元附加到低速比特率A的数据,比特率A的标题。第二标题附加单元将比特率A的报头附加到高速比特率B的数据。 组合单元组合第一和第二插头附接单元的输出。 低速扰频单元通过使用对应于比特率A的时钟对组合数据进行加扰处理。高速扰频单元通过使用与比特率B相对应的时钟对比特率B的数据执行加扰处理 在对应于帧中的比特率A的定时期间,选择器选择低速扰频单元的输出。 在对应于帧中的比特率B的定时期间,选择器选择高速扰频单元的输出。