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    • 5. 发明授权
    • Telephone communication control apparatus, telephone communication system and telephone communication control method used for the same
    • 电话通信控制装置,电话通信系统和电话通信控制方法相同
    • US08885810B2
    • 2014-11-11
    • US12358787
    • 2009-01-23
    • Yoshio Wada
    • Yoshio Wada
    • H04M3/42H04M3/436
    • H04M3/436H04M3/42102H04M3/42153H04M3/42238H04M3/42365
    • A telephone communication control apparatus is provided that ensures a user to be reached by a person who is calling the user without requiring the user to open a number, which identifies the user, to the party. The apparatus includes a registry in which at least status information that indicates status of each of a number of members is registered, wherein the number of members share a fixed telephone terminal and respectively have communication terminals. The apparatus includes— an authentication unit that authenticates a calling subscriber number of a call based on calling subscriber information in which calling subscriber numbers approved to have a session with the members are indicated when the call is made to the number of the fixed telephone terminal. The apparatus includes— a transfer control unit that transfers the call that is authenticated at the authentication unit to a communication terminal based on the information in the registry.
    • 提供了一种电话通信控制装置,其确保用户在呼叫用户的情况下到达用户,而不需要用户向该方打开标识用户的号码。 该装置包括其中登记有至少指示多个成员中的每一个的状态的状态信息的注册表,其中,共享固定电话终端并分别具有通信终端的成员数量。 该装置包括 - 认证单元,其基于主叫用户信息来认证呼叫用户号码,其中当呼叫固定电话终端的号码时,其中指示被批准与会员进行会话的主叫用户号码。 该装置包括 - 传送控制单元,其基于注册表中的信息将在认证单元处认证的呼叫传送到通信终端。
    • 7. 发明申请
    • AUTHENTICATION SYSTEM, SMALL BASE STATION, AND AUTHENTICATION METHOD
    • 认证系统,小基站和认证方法
    • US20110287742A1
    • 2011-11-24
    • US13129896
    • 2009-11-20
    • Katsuhisa NakamuraYoshio WadaKoki HayashiYuichiro Kameoka
    • Katsuhisa NakamuraYoshio WadaKoki HayashiYuichiro Kameoka
    • H04W12/06
    • H04W12/06H04L61/2514H04L63/101H04W84/045
    • The present invention relates to an authentication system, a small base station, and an authentication method which allow a server side to authenticate whether an installation position of a small base station is valid or not. In a packet to be sent as an authentication request from the femto base station 1, in-IC card information of an IC card inserted into the femto base station 1 is contained. A network terminating device 2 converts a local IP address described in a header of the packet to a global IP address, and sends it to a femto concentrator 4. The femto concentrator 4 generates authentication information by associating the in-IC card information with the global IP address, and sends it to an authentication server 5. The authentication server 5 determines that the installation position of the femto base station 1 is valid if the in-IC card information and global IP address included in the authentication information have been associated with each other and registered in an authentication table. The present invention can be applied to a base station for a femtocell.
    • 本发明涉及允许服务器端认证小型基站的安装位置是否有效的认证系统,小型基站和认证方法。 在作为来自毫微微基站1的认证请求发送的分组中,包含插入到毫微微基站1的IC卡的IC卡内信息。 网络终端设备2将分组报头中描述的本地IP地址转换为全局IP地址,并将其发送到毫微微集中器4.毫微微集中器4通过将IC卡内信息与全局IP卡信息相关联来生成认证信息 IP地址,并将其发送给认证服务器5.认证服务器5确定毫微微基站1的安装位置是否有效,如果包含在认证信息中的IC卡内信息和全局IP地址已经与每个 其他并注册在认证表中。 本发明可以应用于毫微微小区的基站。
    • 8. 发明授权
    • PAL chroma signal demodulating apparatus
    • PAL色度信号解调装置
    • US5473388A
    • 1995-12-05
    • US200434
    • 1994-02-23
    • Kazuki TakakiYoshio Wada
    • Kazuki TakakiYoshio Wada
    • H04N5/455H04N11/16H04N9/66
    • H04N11/165
    • A signal demodulator apparatus comprises: an input terminal (11) for inputting an external signal; a delay line (12) connected to the input terminal, for outputting a first delay signal obtained by delaying the external signal by a predetermined time; a phase corrector (13) responsive to the first delay signal outputted by the delay line, for correcting phase of the first delay signal on the basis of a phase difference detection signal and outputting the first phase-corrected delay signal as a second delay signal; and a phase difference detector (16, 15, 19, 20) for detecting a phase difference between the second delay signal outputted by said phase corrector and the external signal inputted through the input terminal and for outputting the phase difference detection signal to the phase corrector to correct the phase difference to a predetermined value. Whenever the delay time of the delay signal disperses due to a manufacturing error or a change with the lapse of time of the delay line (12), it is possible to automatically correct an offset of the phase difference from a normal value.
    • 一种信号解调装置,包括:输入端(11),用于输入外部信号; 连接到输入端的延迟线(12),用于输出通过将外部信号延迟预定时间而获得的第一延迟信号; 响应于延迟线输出的第一延迟信号的相位校正器(13),用于基于相位差检测信号校正第一延迟信号的相位,并将第一相位校正的延迟信号作为第二延迟信号输出; 以及相位差检测器(16,15,19,20),用于检测由所述相位校正器输出的第二延迟信号和通过输入端输入的外部信号之间的相位差,并将相位差检测信号输出到相位校正器 以将相位差校正为预定值。 无论何时延迟信号的延迟时间由于制造误差或随着延迟线(12)的经过时间的改变而分散,可以将相位差的偏移与正常值自动校正。
    • 10. 发明授权
    • Circuit for fast fourier transform operation
    • 电路用于快速傅里叶变换操作
    • US07979485B2
    • 2011-07-12
    • US11641864
    • 2006-12-20
    • Yoshio Wada
    • Yoshio Wada
    • G06F17/14
    • G06F17/142
    • A circuit for a fast Fourier transform (FFT) operation is provided. The FFT operation circuit includes a plurality of butterfly operation units connected in series. Each of the plurality of butterfly operation units reads a signal in the order in which the plurality of butterfly operation units perform complex multiplication, addition, and subtraction, performs complex multiplication of each sequentially read signal by a complex coefficient corresponding to an FFT length and the stage number of the butterfly operation unit, and performs complex addition and subtraction with the complex multiplied signal. In this way, without disposing a plurality of operation circuits corresponding to a radix, FFT operations corresponding to a plurality of FFT lengths can be performed.
    • 提供了一种用于快速傅立叶变换(FFT)操作的电路。 FFT运算电路包括串联连接的多个蝶形运算单元。 多个蝶形运算单元中的每一个按照多个蝶形运算单元执行复数乘法,相加和减法的顺序读取信号,执行每个顺序读取信号的复数乘以与FFT长度对应的复数系数,并且 蝶形运算单元的级数,并用复数乘法信号进行复加减运算。 以这种方式,在不设置与基数相对应的多个运算电路的情况下,可以执行与多个FFT长度对应的FFT运算。