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1. 发明授权

US5378934A Circuit having a master-and-slave and a by-pass 失效
标题翻译：电路具有主从和旁路
公开(公告)号：US5378934A
公开(公告)日：1995-01-03
申请号：US991102
申请日：1992-12-16
申请人： Toshiro Takahashi , Masaaki Ohkawa , Kazuo Koide
发明人： Toshiro Takahashi , Masaaki Ohkawa , Kazuo Koide
IPC分类号： G01R31/317 , G06F11/267 , G11C7/10 , H03K3/012 , H03K3/037 , H03K3/289 , H03K17/56
CPC分类号： G06F11/2236 , G01R31/31701 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C7/1093 , H03K3/012 , H03K3/0372
摘要： Because a bypass circuit BP connected in parallel with serial paths of first and second storage circuits MF and SF has less serially-connected stages of gates incorporated therein than the storage circuits and has shorter information transfer delay of input data to an output terminal 21 than the storage circuits, the bypass circuit BP outputs the information to the output terminal before the outputs of the storage circuits are determined when data supplied to a data input terminal 20 is fetched synchronously with a clock signal CK. The first and second storage circuits MF and SF are master/slave-operated in diagnosis mode, and the output operation of the bypass circuit BP is inhibited according to the states of signals C1 and C2 for controlling their master/slave operations regardless of the clock change of the first control signal CK. Thus, the master/slave operations of the first and second storage circuits MF and SF are assured in the diagnosis mode.
摘要翻译：因为与第一和第二存储电路MF和SF的串行路径并联连接的旁路电路BP与存储电路并入的门的串联级较少，并且输入数据的信息传输延迟比输出端21更短存储电路时，在与时钟信号CK同步地取出提供给数据输入端子20的数据之前，在确定存储电路的输出之前，旁路电路BP将该信息输出到输出端子。第一和第二存储电路MF和SF在诊断模式下被主/从操作，并且根据用于控制其主/从操作的信号C1和C2的状态来禁止旁路电路BP的输出操作，而不管时钟改变第一控制信号CK。因此，在诊断模式中确保第一和第二存储电路MF和SF的主/从操作。

2. 发明授权

US5227674A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5227674A
公开(公告)日：1993-07-13
申请号：US743746
申请日：1991-08-12
申请人： Toshiro Takahashi , Masaaki Ohkawa , Kazuo Koide
发明人： Toshiro Takahashi , Masaaki Ohkawa , Kazuo Koide
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/1093 , G11C7/00 , G11C7/1078 , G11C7/1087
摘要： A flip-flop circuit includes a data input terminal, a data output terminal, a memory circuit and a bypass circuit having a shorter delay time than that of the memory circuit. The memory circuit and the bypass circuit are connected in parallel between the data input terminal and the data output terminal so that the data are outputted to the data output terminal through the bypass circuit when the data are written in the memory circuit. As a result, the delay time of the flip-flop circuit is shortened.
摘要翻译：触发器电路包括数据输入端子，数据输出端子，存储器电路和具有比存储器电路的延迟时间更短的延迟时间的旁路电路。存储器电路和旁路电路并联连接在数据输入端和数据输出端之间，以便当数据被写入存储电路时，通过旁路电路将数据输出到数据输出端。结果，触发器电路的延迟时间缩短。

3. 发明授权

US5455524A CMOS integrated circuit device and data processing system using the same 失效
标题翻译： CMOS集成电路器件和数据处理系统使用相同
公开(公告)号：US5455524A
公开(公告)日：1995-10-03
申请号：US184067
申请日：1994-01-21
申请人： Toyohito Ikeya , Toshiro Takahashi , Kazuo Koide
发明人： Toyohito Ikeya , Toshiro Takahashi , Kazuo Koide
IPC分类号： G11C11/417 , H01L21/82 , H01L27/02 , H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018528 , H01L2224/05553 , H01L2224/49175 , H01L27/0214 , H01L2924/01014 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025
摘要： A CMOS LSI stably operates with high speed ECL LSI's to provide a data processing system. Two power sources of a negative ECL operation voltage and a positive CMOS operation voltage are provided. In a CMOS LSI, input signals of ECL level are successively amplified through an ECL input interface having a p-channel differential amplifier and an n-channel type differential amplifier, fed to the CMOS output buffer circuit and converted to the CMOS level, processed in a CMOS internal circuit, and output at the ECL level through output open-drain MOSFETs. The CMOS LSI is operated by two power sources which are level-shifted in correspondence with the ECL signal amplitude, instead of using ground potential and a positive voltage such as VDD.
摘要翻译： CMOS LSI以高速ECL LSI稳定运行，以提供数据处理系统。提供两个ECL工作电压和正CMOS工作电压的电源。在CMOS LSI中，ECL电平的输入信号通过具有p沟道差分放大器和n沟道型差分放大器的ECL输入接口连续放大，馈送到CMOS输出缓冲电路并转换为CMOS电平， CMOS内部电路，并通过输出开漏MOSFET在ECL电平输出。 CMOS LSI由与ECL信号幅度相对应的电平移位的两个电源来操作，而不是使用接地电位和诸如VDD的正电压。

4. 发明授权

US07030030B2 Method of manufacturing a semiconductor integrated circuit device having a plurality of wiring layers and mask-pattern generation method 失效
标题翻译：制造具有多个布线层的半导体集成电路器件和掩模图案生成方法的方法
公开(公告)号：US07030030B2
公开(公告)日：2006-04-18
申请号：US10688902
申请日：2003-10-21
申请人： Kazuhisa Suzuki , Kazuo Koide , Toshiro Takahashi
发明人： Kazuhisa Suzuki , Kazuo Koide , Toshiro Takahashi
IPC分类号： H01L21/302
CPC分类号： H01L23/5223 , H01L21/31637 , H01L23/5286 , H01L24/06 , H01L27/0207 , H01L27/0629 , H01L27/11807 , H01L28/40 , H01L2224/05554 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A method is provided for manufacturing an integrated circuit device having a plurality of wiring layers including a first wiring layer which is not the upper most layer among the plurality of wiring layers and a second wiring layer higher than the first wiring layer in the plurality of wiring layers. An interlayer dielectric film is provided to cover the first wiring layer. Holes are then formed in the interlayer dielectric film and a mask film is formed to cover some of the holes. Etching using the mask film is then carried out and an insulating film formed on the interlayer dielectric film is removed, including the bottoms and/or insides of the holes. The mask film is then removed and a conductive member is formed inside the holes.
摘要翻译：提供一种用于制造具有多个布线层的集成电路器件的方法，所述布线层包括多个布线层中不是最上层的第一布线层和比多个布线中的第一布线层高的第二布线层层。提供层间绝缘膜以覆盖第一布线层。然后在层间电介质膜中形成孔，并且形成掩模膜以覆盖一些孔。然后进行使用掩模膜的蚀刻，除去形成在层间电介质膜上的绝缘膜，包括孔的底部和/或内部。然后去除掩模膜，并且在孔内形成导电构件。

5. 发明授权

US06232819B1 Semiconductor integrated circuit device and low-amplitude signal receiving method 有权
标题翻译：半导体集成电路器件和低振幅信号接收方法
公开(公告)号：US06232819B1
公开(公告)日：2001-05-15
申请号：US09504076
申请日：2000-02-15
申请人： Toshiro Takahashi , Kazuo Koide
发明人： Toshiro Takahashi , Kazuo Koide
IPC分类号： H03K501
CPC分类号： H03K3/356121
摘要： When signal transmission is performed between two semiconductor integrated circuit devices in synchronization with a clock signal using a small signal amplitude relative to an operating voltage of the two semiconductor integrated circuit devices, a received signal is held in the receiving semiconductor integrated circuit device in synchronization with the clock signal while the small signal amplitude of the held signal is kept substantially without change. The received signal having the small signal amplitude is amplified along a signal transmission path including a combined logic circuit to a subsequent latch circuit of the receiving semiconductor integrated circuit device.
摘要翻译：当使用相对于两个半导体集成电路器件的工作电压的小的信号幅度与时钟信号同步地在两个半导体集成电路器件之间执行信号传输时，接收信号与接收半导体集成电路器件同步地保持在接收半导体集成电路器件中同时保持信号的小信号幅度基本上保持不变。具有小信号幅度的接收信号沿着包括组合逻辑电路的信号传输路径被放大到接收半导体集成电路器件的后续锁存电路。

6. 发明授权

US6087879A Semiconductor integrated circuit device and low-amplitude signal receiving method 失效
标题翻译：半导体集成电路器件和低振幅信号接收方法
公开(公告)号：US6087879A
公开(公告)日：2000-07-11
申请号：US736694
申请日：1996-10-25
申请人： Toshiro Takahashi , Kazuo Koide
发明人： Toshiro Takahashi , Kazuo Koide
IPC分类号： G01R31/28 , H03K3/356 , H03K19/0175 , H03K19/0948 , H03K5/01
CPC分类号： H03K3/356121
摘要： When signal transmission is performed between two semiconductor integrated circuit devices in synchronization with a clock signal using a small signal amplitude relative to an operating voltage of the two semiconductor integrated circuit devices, a received signal is held in the receiving semiconductor integrated circuit device in synchronization with the clock signal while the small signal amplitude of the held signal is kept substantially without change. The received signal having the small signal amplitude is amplified along a signal transmission path including a combined logic circuit to a subsequent latch circuit of the receiving semiconductor integrated circuit device.
摘要翻译：当使用相对于两个半导体集成电路器件的工作电压的小的信号幅度与时钟信号同步地在两个半导体集成电路器件之间执行信号传输时，接收信号与接收半导体集成电路器件同步地保持在接收半导体集成电路器件中同时保持信号的小信号幅度基本上保持不变。具有小信号幅度的接收信号沿着包括组合逻辑电路的信号传输路径被放大到接收半导体集成电路器件的后续锁存电路。

7. 发明授权

US5438281A Semiconductor integrated circuit device and data processing system having an interface with reduced parasitic capacitance 失效
标题翻译：具有降低的寄生电容的接口的半导体集成电路器件和数据处理系统
公开(公告)号：US5438281A
公开(公告)日：1995-08-01
申请号：US136946
申请日：1993-10-18
申请人： Toshiro Takahashi , Kazuo Koide
发明人： Toshiro Takahashi , Kazuo Koide
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G11C11/401 , H01L21/8234 , H01L27/088 , H01L27/118 , H03K19/0175 , H03K19/0185 , H04L25/02 , H03K19/094 , H03K17/16
CPC分类号： H04L25/028 , H01L27/11898 , H03K19/018571 , H03K19/018592 , H04L25/0292 , H04L25/0298
摘要： Data to be processed are transferred by connecting a one-way element having a reduced parasitic capacitance such as the Schottky diode between an output MOSFET having an open drain structure and an output terminal to be connected with a bus line terminated by an impedance element.
摘要翻译：要处理的数据是通过将具有减小的寄生电容的单向元件（例如肖特基二极管）连接到具有开漏结构的输出MOSFET和与由阻抗元件端接的总线连接的输出端子之间传送的。

8. 发明授权

US5311048A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5311048A
公开(公告)日：1994-05-10
申请号：US738133
申请日：1991-07-31
申请人： Toshiro Takahashi , Kazuo Koide
发明人： Toshiro Takahashi , Kazuo Koide
IPC分类号： H01L21/76 , H01L21/82 , H01L21/822 , H01L27/06 , H01L27/092 , H01L27/118 , H01L27/10 , H01L27/15
CPC分类号： H01L27/0928
摘要： Herein disclosed is a semiconductor integrated circuit device, in which a buffer circuit having a MISFET of a second conduction type and arranged in a first region of the principal plane of a semiconductor substrate of a first conduction type is supplied with a first supply voltage and in which an internal circuit having a complementary MISFET and arranged in a second region of the principal plane of the semiconductor substrate different from the first region is supplied with a second supply voltage independent of the first supply voltage at least over the semiconductor substrate and having a potential equal to that of the first supply voltage. The MISFET of the buffer circuit is formed in the principal plane of a well region of a first conduction type formed in the principal plane of the semiconductor substrate. Between the well region of the first conduction type and the semiconductor substrate, there is formed a separating region for separating the two electrically.
摘要翻译：这里公开了一种半导体集成电路器件，其中具有第二导电类型的MISFET并且布置在第一导电类型的半导体衬底的主平面的第一区域中的缓冲电路被提供有第一电源电压，并且其中具有互补MISFET并且布置在与第一区域不同的半导体衬底的主平面的第二区域中的内部电路至少在半导体衬底上提供与第一电源电压无关的第二电源电压，并具有电位等于第一电源电压。缓冲电路的MISFET形成在形成在半导体衬底的主平面中的第一导电类型的阱区的主平面上。在第一导电类型的阱区和半导体衬底之间，形成用于将两者分离的分离区域。

9. 发明授权

US06939617B2 Non-adhesive latex products 失效
标题翻译：无胶乳产品
公开(公告)号：US06939617B2
公开(公告)日：2005-09-06
申请号：US09997467
申请日：2001-11-28
申请人： Kazuo Koide , Takayuki Suzuki , Takahisa Suzuki
发明人： Kazuo Koide , Takayuki Suzuki , Takahisa Suzuki
IPC分类号： A61F13/10 , B29C41/00 , B29C41/14 , B29C41/34 , B29C41/42 , C08J5/02 , C08K3/00 , C08K5/00 , C08L13/02 , B32B25/00
CPC分类号： C08J5/02 , A61F13/105 , B29C41/003 , B29C41/14 , B29C41/34 , B29C41/42 , B29K2105/0064 , B29L2031/753 , C08J2313/00 , C08K3/011 , C08K5/0025 , C08L13/02 , Y10T428/31826 , Y10T428/31855 , C08L2666/14
摘要： The object of the present invention is to provide a non-adhesive clean latex product and a method for manufacturing the same. A non-adhesive clean emulsion latex product is manufactured by adding a carboxyl-group blocking agent to a carboxylated latex or by providing a layer treated with the carboxyl-group blocking agent on one or both surfaces of a film of the carboxylated latex. Further, a non-adhesive, easy-to-wear-and- remove emulsion latex product is manufactured by affording a layer treated with a carboxyl group blocking agent on the inside surface of a carboxylated latex film and providing a chlorination treatment on the outside thereof. Furthermore, a sulfur free, highly durable latex product can be manufactured by adding an aluminate or an aluminumhydroxide gel to the latex. The present invention also provides a non-powered, clean, on-machine wound fingerstall.
摘要翻译：本发明的目的是提供一种非粘性清洁胶乳产品及其制造方法。通过向羧化胶乳中加入羧基封闭剂或通过在羧化胶乳的膜的一个或两个表面上提供用羧基封端剂处理的层来制造非粘性清洁乳液胶乳产品。此外，通过在羧化胶乳膜的内表面上提供用羧基封闭剂处理的层并在其外部提供氯化处理来制造不粘合的易于去除的乳液胶乳产品。此外，可以通过向乳胶中加入铝酸盐或氢氧化铝凝胶来制造无硫，高耐久性的胶乳产品。本发明还提供了一种非动力，清洁的机上伤口指状物。

10. 发明授权

US5038056A Output circuit 失效
标题翻译：输出电路
公开(公告)号：US5038056A
公开(公告)日：1991-08-06
申请号：US515683
申请日：1990-04-26
申请人： Kazuo Koide , Mikio Yamagishi , Kazutaka Mori
发明人： Kazuo Koide , Mikio Yamagishi , Kazutaka Mori
IPC分类号： H03K19/003
CPC分类号： H03K19/00361
摘要： In order to reduce undesirable output noise, an output circuit is provided which includes a first output MOSFET which is interposed between an output terminal and a first power source voltage, and a second output MOSFET which is interposed between the output terminal and a second power source voltage. In particular, in accordance with one aspect of the invention, a feedback circuit is interposed between the output terminal and the gate of the first output MOSFET or/and between the output terminal and the gate of the second output MOSFET to negatively feedback voltage to provide a gentle level change for the output voltage. In other embodiments, a short-circuit arrangement is provided which is interposed between the gate and source of the first output MOSFET or/and between the gate and source of the second output MOSFET. The short-circuit arrangement is temporarily held in a transferring state at the initial stage of a process in which the corresponding first or second output MOSFET is turned on to provide the desired gentle level change.
摘要翻译：为了减少不期望的输出噪声，提供了一种输出电路，其包括介于输出端和第一电源电压之间的第一输出MOSFET，以及插在输出端和第二电源之间的第二输出MOSFET 电压。特别地，根据本发明的一个方面，反馈电路被插入在第一输出MOSFET的输出端和栅极之间或/和第二输出MOSFET的输出端和栅极之间，以反馈电压以提供输出电压的电平变化较小。在其他实施例中，提供了一种短路布置，其插入在第一输出MOSFET的栅极和源极之间或/以及第二输出MOSFET的栅极和源极之间。在相应的第一或第二输出MOSFET导通的过程的初始阶段，短路装置暂时保持在转移状态，以提供期望的缓和电平变化。

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