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1. 发明授权

US07668675B2 Semiconductor integrated circuit and information processing system 失效
标题翻译：半导体集成电路和信息处理系统
公开(公告)号：US07668675B2
公开(公告)日：2010-02-23
申请号：US12129179
申请日：2008-05-29
申请人： Toshio Takita , Jun Ogawa , Yoshihiro Tamura
发明人： Toshio Takita , Jun Ogawa , Yoshihiro Tamura
IPC分类号： G01R25/04
CPC分类号： H03L7/08 , H03K5/19
摘要： In a semiconductor integrated circuit, a counter counts the number of high-speed clock signals that have been generated in a predetermined number of clock cycles of a low-speed clock signal. In synchronization with the low-speed clock signal, the semiconductor integrated circuit compares the counter value and a predetermined value, and judges whether the frequency of the high-speed clock signal has reaches a predetermined frequency. Since variations in the frequency become smaller as the oscillation of a high-speed oscillator stabilizes, the semiconductor integrated circuit detects that the oscillation is stable when the semiconductor integrated circuit has judged affirmatively a plurality of times.
摘要翻译：在半导体集成电路中，计数器对在低速时钟信号的预定数量的时钟周期中产生的高速时钟信号的数量进行计数。与低速时钟信号同步，半导体集成电路将计数器值和预定值进行比较，判断高速时钟信号的频率是否达到预定频率。由于随着高速振荡器的振荡稳定，频率的变化变小，当半导体集成电路多次判断时，半导体集成电路检测到振荡稳定。

2. 发明授权

US08401136B2 Semiconductor integrated circuit and communication system 有权
标题翻译：半导体集成电路与通信系统
公开(公告)号：US08401136B2
公开(公告)日：2013-03-19
申请号：US12570206
申请日：2009-09-30
申请人： Yoshiaki Fujiwara , Toshio Takita
发明人： Yoshiaki Fujiwara , Toshio Takita
IPC分类号： H04L7/00
CPC分类号： G06F1/04 , G06F1/08 , H03K21/38
摘要： Disclosed is a semiconductor integrated circuit for generating a frequency division clock signal that approximates a desired clock signal without increasing a size thereof. The semiconductor integrated circuit masks, for each programmable cycle, a clock signal to be supplied to a transmission clock generation unit 100, thereby delaying a counting operation of a clock counter 101, and setting a timing for extending a transmission clock signal so as to cause a transmission rate of an average frequency of the transmission clock signal to approximate a predetermined transmission rate, wherein the transmission clock generation unit 100 divides a frequency of a clock source signal S301 that is a high-speed clock signal.
摘要翻译：公开了一种半导体集成电路，用于在不增加其尺寸的情况下产生近似所需时钟信号的分频时钟信号。半导体集成电路在每个可编程周期中屏蔽要提供给发送时钟生成单元100的时钟信号，从而延迟时钟计数器101的计数操作，并设置用于延长发送时钟信号的定时，从而使传输时钟信号的平均频率的传输速率接近预定的传输速率，其中传输时钟产生单元100将作为高速时钟信号的时钟源信号S301的频率除除。

3. 发明申请

US20050028149A1 Compiler and computer capable of reducing noise in particular frequency band 审中-公开
标题翻译：能够降低特定频带噪声的编译器和计算机
公开(公告)号：US20050028149A1
公开(公告)日：2005-02-03
申请号：US10899083
申请日：2004-07-27
申请人： Toshio Takita , Takashi Yoneda
发明人： Toshio Takita , Takashi Yoneda
IPC分类号： G06F9/45
CPC分类号： G06F8/4432 , Y02D10/41
摘要： There are provided in a compiler (2) a loop detecting part (6) that detects a loop portion from an intermediate code generated from a source program; a loop program formatting part (7) that generates a loop processing program for the loop portion when the loop detecting part (6) detects the loop portion; and, as a loop process changing part that changes the number of instruction steps required for performing the loop processing program generated by the loop program formatting part (7), a nop instruction adding part (11) that changes the loop processing program into a program to which n nop instructions are added.
摘要翻译：在编译器（2）中提供了从源程序生成的中间代码检测循环部分的循环检测部分（6）环路程序格式化部分（7），当环路检测部分（6）检测到环路部分时，产生用于环路部分的环路处理程序; 并且作为循环处理改变部，其改变由循环程序格式部分（7）生成的执行循环处理程序所需的指令步骤的数量，将循环处理程序改变为程序的nop指令添加部分（11）添加了n个nop指令。

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