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    • 2. 发明授权
    • Client/server database system
    • 客户端/服务器数据库系统
    • US06651070B1
    • 2003-11-18
    • US09605368
    • 2000-06-29
    • Yoko HirashimaSatoshi KikuchiKenta ShigaNorihiko KawakamiToru Ohashi
    • Yoko HirashimaSatoshi KikuchiKenta ShigaNorihiko KawakamiToru Ohashi
    • G06F1730
    • G06F17/30958G06F17/30303Y10S707/99943Y10S707/99945
    • A database link control method and apparatus capable of establishing a link between records related to each other and a database system including a database control function. The data base system includes a function for storing information regarding at least one record and a link relating records to each other holds at least one link generating information item necessary to generate a link to relate records to each other. The database system includes a database server including a storage to store information regarding at least one record and a storage to store links relating records to each other and a database client. The client holds at least one link generating information item necessary to generate a link to relate records to each other.
    • 能够建立彼此相关的记录之间的链接的数据库链接控制方法和装置以及包括数据库控制功能的数据库系统。 数据库系统包括用于存储关于至少一个记录的信息的功能和将记录彼此相关联的链接保持生成链接所必需的至少一个链接以生成链接以将记录相互关联。 数据库系统包括数据库服务器,其包括用于存储关于至少一个记录的信息的存储和用于存储将记录彼此相关联的链接和数据库客户端的存储。 客户端保存至少一个生成链接所必需的链接以产生彼此关联记录的链接。
    • 6. 发明授权
    • Digital-to-analog converter
    • 数模转换器
    • US06853321B2
    • 2005-02-08
    • US10625691
    • 2003-07-24
    • Toru OhashiYuji Yamamoto
    • Toru OhashiYuji Yamamoto
    • H03M1/66H03M3/00H03M3/02
    • H03M3/502
    • A D/A converter includes a ΔΣmodulator applying Delta-Sigma modulation to a digital signal in order to generate a code sequence, and first and second post-filters as a first-order analog low-pass filter, respectively, which is connected in cascade to the subsequent stage of the modulator, in which low-pass filtering on the code sequence is executed so as to output an analog signal. The post-filter is set to have a cutoff frequency which falls in the frequency range from fca to fHa, where the fca is a cutoff frequecy of the post-filter 11 and the fHa is a maximum frequency thereof. Since the respective attenuation characteristics of post-filters are synthesized, an overall attenuation characteristic between the both filters is able to have the characteristics of a desired second-order filter. The synthesized attenuation characteristic allows the D/A converter to simultaneously execute processing such as de-emphasis in the frequency range between the both cutoff frequency, and elimination of high-frequency noises over the frequency range of the cutoff frequency. As a result, the D/A converter with a small circuit scale can be provided.
    • AD / A转换器包括一个DeltaSigmamodulator,它将Delta-Sigma调制应用于数字信号,以产生一个代码序列,第一和第二后置滤波器分别作为一级模拟低通滤波器级联连接 调制器的后续阶段,其中执行码序列上的低通滤波以输出模拟信号。 后置滤波器被设定为具有从fca到fHa的频率范围内的截止频率,其中fca是后置滤波器11的截止频率,fHa是其最大频率。 由于后滤波器的各自的衰减特性被合成,所以两个滤波器之间的整体衰减特性能够具有期望的二阶滤波器的特性。 合成的衰减特性允许D / A转换器同时执行诸如截止频率之间的频率范围内的去加重以及在截止频率的频率范围上消除高频噪声的处理。 结果,可以提供具有小电路规模的D / A转换器。
    • 9. 发明授权
    • Digital filter
    • 数字滤波器
    • US06657482B2
    • 2003-12-02
    • US10144864
    • 2002-05-15
    • Toru Ohashi
    • Toru Ohashi
    • H03B100
    • H03H17/0294H03H17/04H03H2017/0295
    • A digital filter for forming a feedback path including a delay unit, applying a filter operation to an input signal, giving a frequency characteristic having a predetermined time constant, and generating an output signal, is provided with: a selector having a multiplier for implementing time constants in at least two stages, and selecting the connection of the multiplier corresponding to a preset time constant to perform time constant switching; a timing generator for determining the timing when the time constant switching is performed by the selector; and a correction device for correcting the output of the delay unit to suppress variations in the output signal in the determined timing.
    • 一种用于形成包括延迟单元的反馈路径的数字滤波器,向输入信号施加滤波器操作,给出具有预定时间常数的频率特性以及产生输出信号的选择器具有:具有用于实现时间的乘法器的选择器 至少两级的常数,并选择与预设时间常数对应的乘法器的连接以执行时间常数切换; 定时发生器,用于确定由所述选择器执行所述时间常数切换时的定时; 以及校正装置,用于校正延迟单元的输出,以抑制所确定的定时中的输出信号的变化。