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1. 发明授权

US5236810A Process for preparing printed-circuit board 失效
标题翻译：制备印刷电路板的工艺
公开(公告)号：US5236810A
公开(公告)日：1993-08-17
申请号：US592245
申请日：1990-10-03
申请人： Toshio Kondo , Shinsuke Onishi , Naozumi Iwasawa , Sadaaki Hashimoto
发明人： Toshio Kondo , Shinsuke Onishi , Naozumi Iwasawa , Sadaaki Hashimoto
IPC分类号： G03F7/26 , H05K3/06
CPC分类号： G03F7/265 , H05K3/064 , H05K2203/0793 , H05K2203/135
摘要： An improved process for preparing a printed-circuit board, which successively comprises (I) a step of forming a positive photo-sensitive resist film onto a circuit board having a conductive film according to the electrodeposition coating process, (II) a step of irradiating a full dose of an actinic ray onto the positive photo-sensitive resist film through a photomask with which the actinic ray is cut off over a conductive circuit-forming area, (III) a step of developing the resulting resist film, (IV) a step of etching away a deposited copper-clad area, and (V) removing a remaining resist film on the conductive circuit-forming area, the improvement further comprising a step of imparting the resist film in the conductive circuit-forming area an increased alkali resistance prior to development so as to obtain the printed-circuit board having high resolution with good reproductivity without being affected by variations of the developing conditions.
摘要翻译：一种制备印刷电路板的改进方法，其依次包括（I）根据电沉积涂布工艺在具有导电膜的电路板上形成正光敏抗蚀剂膜的步骤，（II）照射步骤通过在导电电路形成区域上切割光化射线的光掩模，将正光敏抗蚀剂膜上的全剂量的光化射线，（III）显影所得抗蚀剂膜的步骤，（IV）蚀刻掉沉积的铜包层区域的步骤，以及（V）去除导电电路形成区域上的剩余抗蚀剂膜，该改进还包括将导电电路形成区域中的抗蚀剂膜赋予增加的耐碱性的步骤在开发之前，以获得具有高分辨率的印刷电路板，具有良好的再现性，而不受显影条件的变化的影响。

2. 发明授权

US5344740A Positive-type photosensitive electrodeposition coating composition containing quinonediazide resin having an anion-forming group and a nitrogen-containing compound and process for producing circuit plate using same 失效
标题翻译：含有具有阴离子形成基团的醌二叠氮化物树脂和含氮化合物的正型光敏电沉积涂料组合物及其制造方法
公开(公告)号：US5344740A
公开(公告)日：1994-09-06
申请号：US879101
申请日：1992-05-04
申请人： Naozumi Iwasawa , Junichi Higashi , Shinsuke Onishi
发明人： Naozumi Iwasawa , Junichi Higashi , Shinsuke Onishi
IPC分类号： G03F7/023 , C09D5/00 , C09D5/44 , C09D133/04 , C25D13/06 , G03F7/022 , H05K3/06 , G03F7/30
CPC分类号： G03F7/0226 , G03F7/023
摘要： A positive-type photosensitive electrodeposition coating composition comprising(A) a resin component containing in a molecule at least one unit selected from the group consisting of an ortho-benzoquinonediazidesulfone unit represented by the general formula ##STR1## an ortho-naphthoquinonediazidesulfone unit represented by the general formula ##STR2## as a photosensitive group, and an anion-forming group; and (B) at least one of the specified particular nitrogen-containing compounds. The composition is useful for the production of a circuit plate.
摘要翻译：一种正型光敏电沉积涂料组合物，其包含（A）在分子中含有至少一个单元的树脂组分，所述单元选自由以下通式表示的邻苯醌二叠氮化物单元：邻苯并醌醌二叠氮化物单元通式成型组; 和（B）至少一种特定的含氮化合物。该组合物可用于生产电路板。

3. 发明申请

US20080071486A1 Semiconductor device with its test time reduced and a test method therefor 有权
标题翻译：其测试时间缩短的半导体器件及其测试方法
公开(公告)号：US20080071486A1
公开(公告)日：2008-03-20
申请号：US11797698
申请日：2007-05-07
申请人： Hideo Ikejiri , Shinsuke Onishi
发明人： Hideo Ikejiri , Shinsuke Onishi
IPC分类号： G06F19/00 , G01R19/00 , G01R21/06
CPC分类号： G01R31/318357 , G01R31/318385
摘要： In a semiconductor device, when a voltage regulator is halted from operating and a test supply voltage is supplied to second logics, the device is initialized by a reset signal. A register included in the device is then reset by an input signal via first logics. The voltage regulator is halted by a power-down signal. Testing is then carried out as the test supply voltage is applied to the second logics. When plural test items are executed successively, a test reset signal is applied to a test reset terminal for each item. As the initialized state of the register is canceled, the first and second logics are initialized.
摘要翻译：在半导体器件中，当电压调节器停止工作并将测试电源电压提供给第二逻辑时，器件由复位信号初始化。然后通过第一逻辑通过输入信号复位器件中包含的寄存器。电压调节器由掉电信号停止。随着测试电源电压被施加到第二逻辑，然后进行测试。当连续执行多个测试项目时，将测试复位信号应用于每个项目的测试复位终端。由于寄存器的初始化状态被取消，初始化第一和第二逻辑。

4. 发明授权

US09192974B2 Work-punching device, work-punching method, and method for producing element for continuously variable transmission 有权
标题翻译：冲孔装置，冲孔方法及无级变速器用元件的制造方法
公开(公告)号：US09192974B2
公开(公告)日：2015-11-24
申请号：US13812819
申请日：2011-07-05
申请人： Naruhiko Okubo , Masaaki Fujita , Shintaro Nakamura , Shinsuke Onishi
发明人： Naruhiko Okubo , Masaaki Fujita , Shintaro Nakamura , Shinsuke Onishi
IPC分类号： B21D28/02 , B21D35/00 , B21D28/06 , B21D28/16 , B21D43/04 , B21D53/14 , F16G5/06
CPC分类号： B21D28/02 , B21D28/06 , B21D28/16 , B21D35/001 , B21D43/04 , B21D53/14 , F16G5/06
摘要： A work-punching device and work-punching method capable of appropriately changing a counter load is provided. Also, a method for manufacturing an element for continuously variable transmission with simple process is provided. A counter load may be controlled by increasing and decreasing a pressure of a fluid, when punching an element 10 from a metal band plate 20 while applying a counter load by a counter punch 113.
摘要翻译：提供了能够适当地改变反荷载的冲孔装置和冲压加工方法。另外，提供了一种用于以简单的方法制造用于无级变速器的元件的方法。当通过反冲头113施加反荷载时，当从金属带板20冲压元件10时，可以通过增加和减小流体的压力来控制反荷载。

5. 发明申请

US20130227999A1 WORKPIECE PUNCH-MOLDING METHOD AND WORKPIECE PUNCH-MOLDING DEVICE 审中-公开
标题翻译：工作冲压成型方法和工件冲压成型装置
公开(公告)号：US20130227999A1
公开(公告)日：2013-09-05
申请号：US13517073
申请日：2011-11-24
申请人： Shinsuke Onishi , Masaaki Fujita , Shintaro Nakamura , Naoya Nemoto , Naruhiko Okubo
发明人： Shinsuke Onishi , Masaaki Fujita , Shintaro Nakamura , Naoya Nemoto , Naruhiko Okubo
IPC分类号： B21D28/02 , B21D28/24
CPC分类号： B21D28/02 , B21D28/16 , B21D28/24
摘要： Provided is a workpiece punch-molding method and a workpiece punch-molding device capable of maintaining the thickness of a workpiece at a constant precision. Prior to the punch of a workpiece by a mold punch and a counter punch, the data denoting a relationship between a punch speed of the mold punch and a delay time of the depressurization of the counter punch is obtained. The counter punch is subjected to the depressurization at an early timing based on the obtained data.
摘要翻译：本发明提供能够以一定的精度保持工件的厚度的工件冲压成型方法和工件冲压成型装置。在通过模具冲头和反冲头冲压工件之前，获得表示冲模冲头速度与计数冲头的减压延迟时间之间的关系的数据。基于所获得的数据，按照早期定时对计数器冲头进行减压。

6. 发明授权

US07724024B2 Semiconductor device with its test time reduced and a test method therefor 有权
标题翻译：其测试时间缩短的半导体器件及其测试方法
公开(公告)号：US07724024B2
公开(公告)日：2010-05-25
申请号：US12479083
申请日：2009-06-26
申请人： Hideo Ikejiri , Shinsuke Onishi
发明人： Hideo Ikejiri , Shinsuke Onishi
IPC分类号： H03K19/00
CPC分类号： G01R31/318357 , G01R31/318385
摘要： In a semiconductor device, when a voltage regulator is halted from operating and a test supply voltage is supplied to second logics, the device is initialized by a reset signal. A register included in the device is then reset by an input signal via first logics. The voltage regulator is halted by a power-down signal. Testing is then carried out as the test supply voltage is applied to the second logics. When plural test items are executed successively, a test reset signal is applied to a test reset terminal for each item. As the initialized state of the register is canceled, the first and second logics are initialized.
摘要翻译：在半导体器件中，当电压调节器停止工作并将测试电源电压提供给第二逻辑时，器件由复位信号初始化。然后通过第一逻辑通过输入信号复位器件中包含的寄存器。电压调节器由掉电信号停止。随着测试电源电压被施加到第二逻辑，然后进行测试。当连续执行多个测试项目时，将测试复位信号应用于每个项目的测试复位终端。由于寄存器的初始化状态被取消，初始化第一和第二逻辑。

7. 发明授权

US07106139B2 Amplification circuit and oscillation circuit including inverter circuits having a same threshold voltage 有权
标题翻译：包括具有相同阈值电压的反相电路的放大电路和振荡电路
公开(公告)号：US07106139B2
公开(公告)日：2006-09-12
申请号：US10173925
申请日：2002-06-19
申请人： Masashi Morimoto , Shinsuke Onishi
发明人： Masashi Morimoto , Shinsuke Onishi
IPC分类号： H03L7/085
CPC分类号： H03F3/345 , H03F3/72 , H03K3/3545
摘要： A first inverter includes a plurality of first gate elements having first gate electrodes which extend in a first direction. A second inverter includes a plurality of second gate elements having second gate electrodes which extend in the first direction. A gate length of the first gate electrodes is the same as a gate length of the second gate electrodes, and a gate width of the first gate electrodes which is defined by a first active region, is the same as a gate width of the second gate electrodes which is defined by a second active region.
摘要翻译：第一反相器包括具有沿第一方向延伸的第一栅电极的多个第一栅极元件。第二反相器包括具有在第一方向上延伸的第二栅电极的多个第二栅极元件。第一栅电极的栅极长度与第二栅电极的栅极长度相同，由第一有源区限定的第一栅电极的栅极宽度与第二栅极的栅极宽度相同由第二活性区域限定的电极。

8. 发明申请

US20130174626A1 WORK-PUNCHING DEVICE, WORK-PUNCHING METHOD, AND METHOD FOR PRODUCING ELEMENT FOR CONTINUOUSLY VARIABLE TRANSMISSION 有权
标题翻译：工作打孔装置，工作打孔方法和用于生成连续可变传动元件的方法
公开(公告)号：US20130174626A1
公开(公告)日：2013-07-11
申请号：US13812819
申请日：2011-07-05
申请人： Naruhiko Okubo , Masaaki Fujita , Shintaro Nakamura , Shinsuke Onishi
发明人： Naruhiko Okubo , Masaaki Fujita , Shintaro Nakamura , Shinsuke Onishi
IPC分类号： B21D28/02 , B21D43/04
CPC分类号： B21D28/02 , B21D28/06 , B21D28/16 , B21D35/001 , B21D43/04 , B21D53/14 , F16G5/06
摘要： A work-punching device and work-punching method capable of appropriately changing a counter load is provided. Also, a method for manufacturing an element for continuously variable transmission with simple process is provided. A counter load may be controlled by increasing and decreasing a pressure of a fluid, when punching an element 10 from a metal band plate 20 while applying a counter load by a counter punch 113.
摘要翻译：提供了能够适当地改变反荷载的冲孔装置和冲压加工方法。另外，提供了一种用于以简单的方法制造用于无级变速器的元件的方法。当通过反冲头113施加反荷载时，当从金属带板20冲压元件10时，可以通过增加和减小流体的压力来控制反荷载。

9. 发明授权

US07564265B2 Semiconductor device with its test time reduced and a test method therefor 有权
标题翻译：其测试时间缩短的半导体器件及其测试方法
公开(公告)号：US07564265B2
公开(公告)日：2009-07-21
申请号：US11797698
申请日：2007-05-07
申请人： Hideo Ikejiri , Shinsuke Onishi
发明人： Hideo Ikejiri , Shinsuke Onishi
IPC分类号： H03K19/00
CPC分类号： G01R31/318357 , G01R31/318385
摘要： In a semiconductor device, when a voltage regulator is halted from operating and a test supply voltage is supplied to second logics, the device is initialized by a reset signal. A register included in the device is then reset by an input signal via first logics. The voltage regulator is halted by a power-down signal. Testing is then carried out as the test supply voltage is applied to the second logics. When plural test items are executed successively, a test reset signal is applied to a test reset terminal for each item. As the initialized state of the register is canceled, the first and second logics are initialized.
摘要翻译：在半导体器件中，当电压调节器停止工作并将测试电源电压提供给第二逻辑时，器件由复位信号初始化。然后通过第一逻辑通过输入信号复位器件中包含的寄存器。电压调节器由掉电信号停止。随着测试电源电压被施加到第二逻辑，然后进行测试。当连续执行多个测试项目时，将测试复位信号应用于每个项目的测试复位终端。由于寄存器的初始化状态被取消，初始化第一和第二逻辑。

10. 发明授权

US07557604B2 Input circuit for mode setting 失效
标题翻译：模式设定输入电路
公开(公告)号：US07557604B2
公开(公告)日：2009-07-07
申请号：US11119899
申请日：2005-05-03
申请人： Shinsuke Onishi , Tsuguto Maruko
发明人： Shinsuke Onishi , Tsuguto Maruko
IPC分类号： H03K19/177
CPC分类号： H03K19/1732
摘要： An input circuit for mode setting, comprising: a chip selection terminal that is operable both in first and second operation modes; a mode setting terminal that is used to select an operation mode from between the first and second operation modes; a logic holding circuit that holds a logic status at the mode setting terminal; and a control circuit that controls the logic holding circuit in accordance with a signal supplied to the chip selection terminal. Operation modes to be selected may be serial interface mode and parallel interface mode.
摘要翻译：一种用于模式设置的输入电路，包括：芯片选择端子，其可在第一和第二操作模式中操作; 用于从第一和第二操作模式之间选择操作模式的模式设置终端; 逻辑保持电路，在模式设定端子保持逻辑状态; 以及根据提供给芯片选择端的信号来控制逻辑保持电路的控制电路。要选择的操作模式可以是串行接口模式和并行接口模式。

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