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1. 发明申请

US20080233736A1 PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：制造半导体集成电路器件的工艺
公开(公告)号：US20080233736A1
公开(公告)日：2008-09-25
申请号：US12127564
申请日：2008-05-27
申请人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
发明人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
IPC分类号： H01L21/4763
CPC分类号： H01L21/0209 , G09G5/399 , H01L21/02074 , H01L21/3212 , H01L21/76838 , H01L21/7684 , Y10S438/906
摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.
摘要翻译：为了提供通过化学机械抛光（CMP）方法形成的金属配线的防腐蚀技术，根据本发明的半导体集成电路器件的制造方法包括以下步骤：形成Cu（或Cu合金）的金属层含有Cu作为主要成分），然后通过化学机械抛光（CMP）方法平坦化金属层以形成金属布线; 防止晶片的平面化主面在金属布线的表面上形成疏水性保护膜; 将晶圆的防腐主面浸入或保持湿润状态，使其不会变干; 并将晶片的主要表面保持在潮湿状态。

2. 发明申请

US20060141792A1 Process for manufacturing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件制造工艺
公开(公告)号：US20060141792A1
公开(公告)日：2006-06-29
申请号：US11357181
申请日：2006-02-21
申请人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
发明人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
IPC分类号： H01L21/44
CPC分类号： H01L21/0209 , G09G5/399 , H01L21/02074 , H01L21/3212 , H01L21/76838 , H01L21/7684 , Y10S438/906
摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP). method, a process for manufacturing. a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.
摘要翻译：为了提供通过化学机械抛光（CMP）形成的金属配线的防腐蚀技术。方法，制造方法。根据本发明的半导体集成电路器件包括以下步骤：在晶片的主面上形成Cu（或含有Cu作为主要成分的Cu合金）的金属层，然后通过化学机械抛光使金属层平坦化（CMP）方法形成金属布线; 防止晶片的平面化主面在金属布线的表面上形成疏水性保护膜; 将晶圆的防腐主面浸入或保持湿润状态，使其不会变干; 并将晶片的主要表面保持在潮湿状态。

3. 发明授权

US06800557B2 Process for manufacturing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件制造工艺
公开(公告)号：US06800557B2
公开(公告)日：2004-10-05
申请号：US10369716
申请日：2003-02-21
申请人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
发明人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
IPC分类号： H01L21302
CPC分类号： H01L21/0209 , G09G5/399 , H01L21/02074 , H01L21/3212 , H01L21/76838 , H01L21/7684 , Y10S438/906
摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.
摘要翻译：为了提供通过化学机械抛光（CMP）方法形成的金属配线的防腐蚀技术，根据本发明的半导体集成电路器件的制造方法包括以下步骤：形成Cu（或Cu合金）的金属层含有Cu作为主要成分），然后通过化学机械抛光（CMP）方法平坦化金属层以形成金属布线; 防止晶片的平面化主面在金属布线的表面上形成疏水性保护膜; 将晶圆的防腐主面浸入或保持湿润状态，使其不会变干; 并将晶片的主要表面保持在潮湿状态。

4. 发明授权

US07510970B2 Process for manufacturing semiconductor integrated circuit device 有权
公开(公告)号：US07510970B2
公开(公告)日：2009-03-31
申请号：US11357181
申请日：2006-02-21
申请人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
发明人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
IPC分类号： H01L21/44
CPC分类号： H01L21/0209 , G09G5/399 , H01L21/02074 , H01L21/3212 , H01L21/76838 , H01L21/7684 , Y10S438/906
摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

5. 发明授权

US06326299B1 Method for manufacturing a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US06326299B1
公开(公告)日：2001-12-04
申请号：US09361989
申请日：1999-07-28
申请人： Yoshio Homma , Seiichi Kondo , Noriyuki Sakuma , Naofumi Ohashi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada
发明人： Yoshio Homma , Seiichi Kondo , Noriyuki Sakuma , Naofumi Ohashi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada
IPC分类号： H01L214763
CPC分类号： H01L21/3212 , C09G1/02 , H01L21/7684
摘要： In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.
摘要翻译：为了抑制在绝缘膜中形成的槽中以镶嵌法形成铜基合金镶嵌布线时在抛光期间在铜基合金层上发生的凹陷等的增加，下金属层的研磨速度设定为比其蚀刻速度快五倍以上，并且当上金属层13成为布线时，绝缘膜的抛光速率被设定为低于下金属层的抛光速率，下金属层 12成为屏障分别抛光。因此，对象镶嵌布线可以分别形成在绝缘层和每个金属层上的凹陷上较少的侵蚀。

6. 发明授权

US06509273B1 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US06509273B1
公开(公告)日：2003-01-21
申请号：US09527751
申请日：2000-03-17
申请人： Toshinori Imai , Naofumi Ohashi , Yoshio Homma , Seiichi Kondo
发明人： Toshinori Imai , Naofumi Ohashi , Yoshio Homma , Seiichi Kondo
IPC分类号： H01L21302
CPC分类号： H01L21/7684 , H01L21/02074 , H01L21/3212
摘要： Problematic dishing and erosion in forming embedded metal interconnection by a chemical mechanical polishing (CMP) method are suppressed. Formation of embedded Cu interconnects 46a to 46e by chemical mechanical polishing of a Cu film 46 formed in interconnect trenches 40 to 44 is performed by abrasive-grain-free chemical mechanical polishing using a polishing liquid of an abrasive grain content less than 0.5 wt % (CMP of the first step); with-abrasive-grain chemical mechanical polishing using a polishing liquid of an abrasive grain content of 0.5 or more wt % (CMP of the second step); and selective chemical mechanical polishing using a polishing liquid to which an anticorrosive such as benzotriazole (BTA) is added (CMP of the third step).
摘要翻译：通过化学机械抛光（CMP）方法形成嵌入金属互连的问题的凹陷和侵蚀被抑制。通过在互连沟槽40至44中形成的Cu膜46的化学机械抛光来形成嵌入的Cu互连46a至46e，使用磨料颗粒含量小于0.5重量％（第一步骤的CMP）的抛光液的无颗粒化学机械抛光; 使用磨料颗粒含量为0.5重量％以上的研磨液（第二工序的CMP）进行磨粒化学机械研磨; 以及使用添加了抗腐蚀剂如苯并三唑（BTA）的抛光液进行选择性化学机械抛光（第三步骤的CMP）。

7. 发明授权

US06376345B1 Process for manufacturing semiconductor integrated circuit device 有权
公开(公告)号：US06376345B1
公开(公告)日：2002-04-23
申请号：US09356707
申请日：1999-07-20
申请人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
发明人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
IPC分类号： H01L2138
CPC分类号： H01L21/0209 , G09G5/399 , H01L21/02074 , H01L21/3212 , H01L21/76838 , H01L21/7684 , Y10S438/906
摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

8. 发明授权

US07659201B2 Process for manufacturing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件制造工艺
公开(公告)号：US07659201B2
公开(公告)日：2010-02-09
申请号：US12127564
申请日：2008-05-27
申请人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
发明人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
IPC分类号： H01L21/44
CPC分类号： H01L21/0209 , G09G5/399 , H01L21/02074 , H01L21/3212 , H01L21/76838 , H01L21/7684 , Y10S438/906
摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.
摘要翻译：为了提供通过化学机械抛光（CMP）方法形成的金属配线的防腐蚀技术，根据本发明的半导体集成电路器件的制造方法包括以下步骤：形成Cu（或Cu合金）的金属层含有Cu作为主要成分），然后通过化学机械抛光（CMP）方法平坦化金属层以形成金属布线; 防止晶片的平面化主面在金属布线的表面上形成疏水性保护膜; 将晶圆的防腐主面浸入或保持湿润状态，使其不会变干; 并将晶片的主要表面保持在潮湿状态。

9. 发明授权

US06638854B2 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US06638854B2
公开(公告)日：2003-10-28
申请号：US10227284
申请日：2002-08-26
申请人： Yoshio Homma , Seiichi Kondo , Noriyuki Sakuma , Naofumi Ohashi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada
发明人： Yoshio Homma , Seiichi Kondo , Noriyuki Sakuma , Naofumi Ohashi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada
IPC分类号： H01L214763
CPC分类号： H01L21/3212 , C09G1/02 , H01L21/7684
摘要： In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.

10. 发明授权

US06458674B1 Process for manufacturing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件制造工艺
公开(公告)号：US06458674B1
公开(公告)日：2002-10-01
申请号：US10050562
申请日：2002-01-18
申请人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
发明人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
IPC分类号： H01L21/3205 , G09G5/399 , H01L21/02 , H01L21/302 , H01L21/304 , H01L21/321 , H01L21/768 , H01L21/38
CPC分类号： H01L21/0209 , G09G5/399 , H01L21/02074 , H01L21/3212 , H01L21/76838 , H01L21/7684 , Y10S438/906
摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the resurfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.
摘要翻译：为了提供通过化学机械抛光（CMP）方法形成的金属配线的防腐蚀技术，根据本发明的半导体集成电路器件的制造方法包括以下步骤：形成Cu（或Cu合金）的金属层含有Cu作为主要成分），然后通过化学机械抛光（CMP）方法平坦化金属层以形成金属布线; 防止晶片的平面化主面在金属布线的表面上形成疏水性保护膜; 将晶圆的防腐主面浸入或保持湿润状态，使其不会变干; 并将晶片的主要表面保持在潮湿状态。

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