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1. 发明授权

US08482974B2 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US08482974B2
公开(公告)日：2013-07-09
申请号：US13022292
申请日：2011-02-07
申请人： Toshihiko Saito , Takanori Matsuzaki , Shuhei Nagatsuka , Hiroki Inoue
发明人： Toshihiko Saito , Takanori Matsuzaki , Shuhei Nagatsuka , Hiroki Inoue
IPC分类号： G11C11/14
CPC分类号： G11C11/405 , H01L27/11521 , H01L27/1156 , H01L27/1225 , H01L28/40
摘要： A semiconductor device includes a first signal line, a second signal line, a memory cell, and a potential converter circuit. The memory cell includes a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region; and a capacitor. The first channel formation region and the second channel formation region include different semiconductor materials. The second drain electrode, one electrode of the capacitor, and the first gate electrode are electrically connected to one another. The second gate electrode is electrically connected to the potential converter circuit through the second signal line.
摘要翻译：半导体器件包括第一信号线，第二信号线，存储单元和电位转换器电路。存储单元包括：第一晶体管，包括第一栅极电极，第一源电极，第一漏极电极和第一沟道形成区域; 第二晶体管，包括第二栅极电极，第二源极电极，第二漏极电极和第二沟道形成区域; 和电容器。第一沟道形成区域和第二沟道形成区域包括不同的半导体材料。第二漏电极，电容器的一个电极和第一栅电极彼此电连接。第二栅极通过第二信号线电连接到电位转换器电路。

2. 发明授权

US08406038B2 Semiconductor device 有权
公开(公告)号：US08406038B2
公开(公告)日：2013-03-26
申请号：US13094863
申请日：2011-04-27
申请人： Toshihiko Saito , Takanori Matsuzaki , Shuhei Nagatsuka , Hiroki Inoue
发明人： Toshihiko Saito , Takanori Matsuzaki , Shuhei Nagatsuka , Hiroki Inoue
IPC分类号： G11C11/24
CPC分类号： H01L29/78 , G11C11/403 , G11C11/406 , G11C16/0416 , G11C2211/4065 , H01L27/11521 , H01L27/1156 , H01L27/1207 , H01L27/1225
摘要： A semiconductor device includes a plurality of memory cells including a first transistor and a second transistor, a reading circuit including an amplifier circuit and a switch element, and a refresh control circuit. A first channel formation region and a second channel formation region contain different materials as their respective main components. A first gate electrode is electrically connected to one of a second source electrode and a second drain electrode. The other of the second source electrode and the second drain electrode is electrically connected to one of input terminals of the amplifier circuit. An output terminal of the amplifier circuit is connected to the other of the second source electrode and the second drain electrode through the switch element. The refresh control circuit is configured to control whether the switch element is turned on or off.

3. 发明申请

US20110199807A1 SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME 有权
标题翻译：半导体器件及其驱动方法
公开(公告)号：US20110199807A1
公开(公告)日：2011-08-18
申请号：US13022292
申请日：2011-02-07
申请人： Toshihiko Saito , Takanori Matsuzaki , Shuhei Nagatsuka , Hiroki Inoue
发明人： Toshihiko Saito , Takanori Matsuzaki , Shuhei Nagatsuka , Hiroki Inoue
IPC分类号： G11C5/06 , H01L29/12
CPC分类号： G11C11/405 , H01L27/11521 , H01L27/1156 , H01L27/1225 , H01L28/40
摘要： A semiconductor device includes a first signal line, a second signal line, a memory cell, and a potential converter circuit. The memory cell includes a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region; and a capacitor. The first channel formation region and the second channel formation region include different semiconductor materials. The second drain electrode, one electrode of the capacitor, and the first gate electrode are electrically connected to one another. The second gate electrode is electrically connected to the potential converter circuit through the second signal line.
摘要翻译：半导体器件包括第一信号线，第二信号线，存储单元和电位转换器电路。存储单元包括：第一晶体管，包括第一栅极电极，第一源电极，第一漏极电极和第一沟道形成区域; 第二晶体管，包括第二栅极电极，第二源极电极，第二漏极电极和第二沟道形成区域; 和电容器。第一沟道形成区域和第二沟道形成区域包括不同的半导体材料。第二漏电极，电容器的一个电极和第一栅电极彼此电连接。第二栅极通过第二信号线电连接到电位转换器电路。

4. 发明申请

US20110228602A1 MEMORY DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：存储器件和半导体器件
公开(公告)号：US20110228602A1
公开(公告)日：2011-09-22
申请号：US13044656
申请日：2011-03-10
申请人： Toshihiko Saito , Shuhei Nagatsuka
发明人： Toshihiko Saito , Shuhei Nagatsuka
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： G11C16/26 , G11C11/404 , G11C11/405 , G11C14/00 , G11C16/0433
摘要： One of objects is to provide a nonvolatile memory device in which the occurrence of a defect in data writing is suppressed and whose area can be suppressed, or a semiconductor device including the nonvolatile memory device. A first memory portion including a nonvolatile memory element and a second memory portion (data buffer) for temporarily storing data in verifying operation in which whether the data is correctly written into the first memory portion is verified are provided. Further, the second memory portion includes a memory element and an insulated gate field effect transistor for controlling the holding of charge in the memory element; the off-state current or the leakage current of the transistor is extremely low.
摘要翻译：其目的之一是提供一种非易失性存储器件，其中数据写入中的缺陷的发生被抑制并且其面积可被抑制，或者包括非易失性存储器件的半导体器件。提供了一种包括非易失性存储元件和用于临时存储数据的第二存储器部分（数据缓冲器）的第一存储器部分，其被验证是否将数据正确写入第一存储器部分的验证操作。此外，第二存储器部分包括用于控制存储元件中的电荷的保持的存储元件和绝缘栅场效应晶体管; 晶体管的截止电流或漏电流极低。

5. 发明授权

US08422298B2 Memory device and semiconductor device 有权
标题翻译：存储器件和半导体器件
公开(公告)号：US08422298B2
公开(公告)日：2013-04-16
申请号：US13044656
申请日：2011-03-10
申请人： Toshihiko Saito , Shuhei Nagatsuka
发明人： Toshihiko Saito , Shuhei Nagatsuka
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： G11C16/26 , G11C11/404 , G11C11/405 , G11C14/00 , G11C16/0433
摘要： One of objects is to provide a nonvolatile memory device in which the occurrence of a defect in data writing is suppressed and whose area can be suppressed, or a semiconductor device including the nonvolatile memory device. A first memory portion including a nonvolatile memory element and a second memory portion (data buffer) for temporarily storing data in verifying operation in which whether the data is correctly written into the first memory portion is verified are provided. Further, the second memory portion includes a memory element and an insulated gate field effect transistor for controlling the holding of charge in the memory element; the off-state current or the leakage current of the transistor is extremely low.
摘要翻译：其目的之一是提供一种非易失性存储器件，其中数据写入中的缺陷的发生被抑制并且其面积可被抑制，或者包括非易失性存储器件的半导体器件。提供了一种包括非易失性存储元件和用于临时存储数据的第二存储器部分（数据缓冲器）的第一存储器部分，其被验证是否将数据正确写入第一存储器部分的验证操作。此外，第二存储器部分包括用于控制存储元件中的电荷的保持的存储元件和绝缘栅场效应晶体管; 晶体管的截止电流或漏电流极低。

6. 发明授权

US08264874B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08264874B2
公开(公告)日：2012-09-11
申请号：US12890856
申请日：2010-09-27
申请人： Toshihiko Saito , Takanori Matsuzaki
发明人： Toshihiko Saito , Takanori Matsuzaki
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C17/16 , G11C2213/33 , G11C2213/34 , G11C2213/79 , H01L27/24
摘要： Objects of the present invention are to improve the manufacturing yield of semiconductor devices, reduce manufacturing cost of the semiconductor device, and reduce the circuit area of an integrated circuit included in the semiconductor device. A memory layer of a memory element and a resistive layer of a resistor included in the semiconductor device are formed of the same material. Therefore, the memory layer and the resistive layer are formed in the same step, whereby the number of manufacturing steps of the semiconductor device can be reduced. As a result, the manufacturing yield of the semiconductor devices can be improved and the manufacturing cost can be reduced. In addition, the semiconductor device includes a resistor having a resistive component which has high resistance value. Consequently, the area of the integrated circuit included in the semiconductor device can be reduced.
摘要翻译：本发明的目的是提高半导体器件的制造成品率，降低半导体器件的制造成本，并且减小包括在半导体器件中的集成电路的电路面积。存储元件的存储层和包含在半导体器件中的电阻器的电阻层由相同的材料形成。因此，在相同的步骤中形成存储层和电阻层，从而可以减少半导体器件的制造步骤的数量。结果，可以提高半导体器件的制造成品率，并且可以降低制造成本。此外，半导体器件包括具有高电阻值的电阻元件的电阻器。因此，可以减少包括在半导体器件中的集成电路的面积。

7. 发明授权

US08878270B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08878270B2
公开(公告)日：2014-11-04
申请号：US13443928
申请日：2012-04-11
申请人： Toshihiko Saito
发明人： Toshihiko Saito
IPC分类号： H01L31/18 , H01L49/02 , H01L29/786 , H01L27/02 , H01L27/12 , H01L21/84 , H01L27/108
CPC分类号： H01L29/7869 , H01L21/84 , H01L27/0288 , H01L27/10876 , H01L27/10891 , H01L27/1203 , H01L28/60 , H01L28/86 , H01L28/90
摘要： A semiconductor memory device including a bit line, a word line, a transistor, and a capacitor is provided. The transistor includes source and drain electrodes; an oxide semiconductor film in contact with at least both top surfaces of the source and drain electrodes; a gate insulating film in contact with at least a top surface of the oxide semiconductor film; a gate electrode which overlaps with the oxide semiconductor film with the gate insulating film provided therebetween; and an insulating film covering the source and drain electrodes, the gate insulating film, and the gate electrode. The transistor is provided in a mesh of a netlike conductive film when seen from the above. Here, the drain electrode and the netlike conductive film serve as one and the other of a pair of capacitor electrodes of the capacitor. A dielectric film of the capacitor includes at least the insulating film.
摘要翻译：提供了包括位线，字线，晶体管和电容器的半导体存储器件。晶体管包括源极和漏极; 与所述源极和漏极的至少两个顶表面接触的氧化物半导体膜; 与所述氧化物半导体膜的至少顶面接触的栅极绝缘膜; 与所述氧化物半导体膜重叠的栅电极，其间设置有所述栅极绝缘膜; 以及覆盖源极和漏极，栅极绝缘膜和栅电极的绝缘膜。当从上面看时，晶体管设置在网状导电膜的网格中。这里，漏电极和网状导电膜用作电容器的一对电容器电极中的一个和另一个。电容器的电介质膜至少包括绝缘膜。

8. 发明授权

US08820047B2 Combustion burner 有权
公开(公告)号：US08820047B2
公开(公告)日：2014-09-02
申请号：US12743315
申请日：2008-10-30
申请人： Toshihiko Saito , Koichi Ishizaka , Satoshi Tanimura
发明人： Toshihiko Saito , Koichi Ishizaka , Satoshi Tanimura
IPC分类号： F02C3/30 , F23R3/14 , F23R3/28 , F02C7/22
CPC分类号： F23R3/283 , F02C3/30 , F02C3/305 , F02C7/22 , F23R3/14 , F23R3/38 , F23R2900/00004 , Y02T50/675
摘要： A combustion burner 10A according to one embodiment of the present invention includes: a fuel nozzle 110; a burner tube 120 forming the air passage 111 between the burner tube 120 and the fuel nozzle 110; swirler vanes (swirler vanes) 130 arranged in a plurality of positions in the circumferential direction on the external circumferential surface of the fuel nozzle 110, each extending along the axial direction of the fuel nozzle 110, and gradually curving from upstream toward downstream; and a liquid fuel injecting hole 133A from which a liquid fuel is injected to a surface of each of the swirler vanes 130. The combustion burner 10A also includes multi-purpose injecting holes 11-1 to 11-3 as a cooling unit that cools a part of a vane pressure surface 132a of the swirler vane 130 on which the liquid fuel LF hits. Water is injected through the multi-purpose injecting holes 11-1 to 11-3 to form a water film 15A on the vane pressure surface 132a, whereby a combustion temperature is reduced and formation of carbon deposit is prevented.

9. 发明授权

US08767443B2 Semiconductor memory device and method for inspecting the same 有权
标题翻译：半导体存储器件及其检测方法
公开(公告)号：US08767443B2
公开(公告)日：2014-07-01
申请号：US13235967
申请日：2011-09-19
申请人： Toshihiko Saito
发明人： Toshihiko Saito
IPC分类号： G11C11/24
CPC分类号： G11C16/26 , G11C11/403 , G11C11/404 , G11C16/0433
摘要： When the threshold voltage Vth of the transistor in the memory cell is within the allowable range is determined, a memory cell which does not have sufficient data retention characteristics is eliminated. In order to eliminate such a memory cell, the potential of a gate of the transistor is kept at an appropriate potential VGM and the potential of a drain of the transistor is set higher than or equal to VGM. When data is written to the memory cell in this state, the potential of a source of the transistor is expressed as a formula including the threshold voltage Vth, (VGM−Vth). By comparison between the level of the potential and the level of a reference potential, whether the threshold voltage Vth is within the allowable range can be determined.
摘要翻译：当确定存储单元中的晶体管的阈值电压Vth在允许范围内时，消除了不具有足够数据保持特性的存储单元。为了消除这种存储单元，晶体管的栅极的电位保持在适当的电位VGM，并且晶体管的漏极的电位被设置为高于或等于VGM。当在该状态下将数据写入存储单元时，晶体管的源极的电位被表示为包括阈值电压Vth（VGM-Vth）的公式。通过比较电位的电平和参考电位的电平，可以确定阈值电压Vth是否在容许范围内。

10. 发明授权

US08709889B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08709889B2
公开(公告)日：2014-04-29
申请号：US13471667
申请日：2012-05-15
申请人： Toshihiko Saito
发明人： Toshihiko Saito
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L29/7869 , G11C11/404 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/84 , H01L27/1156 , H01L27/1207 , H01L27/1225
摘要： A memory cell therein includes a first transistor and a capacitor and stores data corresponding to a potential held in the capacitor. The first transistor includes a pair of electrodes, an insulating film in contact with side surfaces of the electrodes, a first gate electrode provided between the electrodes with the insulating film provided between the first gate electrode and each electrode and whose top surface is at a lower level than top surfaces of the electrodes, a first gate insulating film over the first gate electrode, an oxide semiconductor film in contact with the first gate insulating film and the electrodes, a second gate insulating film at least over the oxide semiconductor film, and a second gate electrode over the oxide semiconductor film with the second gate insulating film provided therebetween. The capacitor is connected to the first transistor through one of the electrodes.
摘要翻译：其中的存储单元包括第一晶体管和电容器，并且存储对应于保持在电容器中的电位的数据。所述第一晶体管包括一对电极，与所述电极的侧面接触的绝缘膜，设置在所述电极之间的第一栅电极，所述绝缘膜设置在所述第一栅电极与每个电极之间，并且其顶表面处于下部比第一栅极电极上的第一栅极绝缘膜，与第一栅极绝缘膜和电极接触的氧化物半导体膜，至少在氧化物半导体膜上的第二栅极绝缘膜，和第二栅极电极在氧化物半导体膜上方，其间设置有第二栅极绝缘膜。电容器通过其中一个电极连接到第一晶体管。

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