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1. 发明专利

JP2012022739A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2012022739A
公开(公告)日：2012-02-02
申请号：JP2010158700
申请日：2010-07-13
申请人： Toshiba Corp , 株式会社東芝
发明人： SUZUKI AZUMA , YABE TOMOAKI , TACHIBANA FUMIHIKO
IPC分类号： G11C11/41
CPC分类号： G11C11/413
摘要： PROBLEM TO BE SOLVED: To reduce power consumption while enabling handling of write disturbance using a write-back method.SOLUTION: A semiconductor memory device comprises a memory cell 2, a write-back determination part 7, and a readout control part 8. The memory cell 2 can perform writing and reading via different paths. The write-back determination part 7 determines, when a selected column is written, whether a write-back is to be performed for a deselected column. The readout control part 8 controls readout of data used for the write-back for the deselected column, on the basis of the determination result obtained by the write-back determination part 7.
摘要翻译：要解决的问题：降低功耗，同时使用回写方法处理写入干扰。解决方案：半导体存储器件包括存储器单元2，回写确定部件7和读出控制部件8.存储器单元2可以通过不同的通路进行写入和读取。回写确定部件7在写入所选择的列时确定是否对取消选择的列执行回写。读出控制部分8基于由回写确定部分7获得的确定结果控制用于取消列的回写的数据的读出。（C）2012，JPO＆INPIT

2. 发明专利

JP2008234806A Semiconductor memory device and its redundancy method 审中-公开
标题翻译：半导体存储器件及其冗余方法
公开(公告)号：JP2008234806A
公开(公告)日：2008-10-02
申请号：JP2007077306
申请日：2007-03-23
申请人： Toshiba Corp , 株式会社東芝
发明人： YABE TOMOAKI
IPC分类号： G11C11/413
CPC分类号： G11C15/04 , G11C15/046 , G11C29/846
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device for preventing an increase in area even when a large-capacity redundancy is mounted, and to provide its redundancy method.
SOLUTION: The semiconductor memory device is provided with a first memory 11 for receiving a first address and first input data and outputting first output data, an associative memory 13 for receiving the first address as a search address to determine whether or not the first address coincides with a defective address, and outputting a second address and a control signal when coincides, a second memory 12 for outputting redundancy data corresponding to the second address when the second address is input, and a multiplexer 14 for switching the first output data to the redundancy data to output it to an I/O terminal when the control signal is input.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储器件，即使在安装大容量冗余时也防止面积增加，并提供其冗余方法。解决方案：半导体存储器件设置有用于接收第一地址和第一输入数据并输出第一输出数据的第一存储器11，用于接收第一地址作为搜索地址的关联存储器13，以确定是否第一地址与缺陷地址一致，当符合时输出第二地址和控制信号;第二存储器12，用于在输入第二地址时输出与第二地址对应的冗余数据;以及多路复用器14，用于切换第一输出数据到冗余数据以在输入控制信号时将其输出到I / O端子。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2008146734A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2008146734A
公开(公告)日：2008-06-26
申请号：JP2006331992
申请日：2006-12-08
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKANO TAKESHI , YABE TOMOAKI , OTSUKA NOBUAKI
IPC分类号： G11C11/41
CPC分类号： G11C7/18
摘要： PROBLEM TO BE SOLVED: To increase the operation speed of a semiconductor memory.
SOLUTION: This semiconductor memory has sub-arrays connecting the memory cells arranged in matrixes, local bit lines connected to memory cells arranged in the column direction in the sub-arrays, global bit lines connected to the local bit lines, and a column decoder connected to the global bit lines. However, in the farthest sub-array formed in an area most apart from the column decoder among those sub-arrays, the global bit lines are not formed.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提高半导体存储器的操作速度。解决方案：该半导体存储器具有连接以矩阵排列的存储单元的子阵列，连接到子阵列中的列方向上布置的存储单元的本地位线，连接到局部位线的全局位线，以及列解码器连接到全局位线。然而，在这些子阵列中与列解码器最远的区域中形成的最远的子阵列中，不形成全局位线。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2003274945A Hybridization detection device 有权
标题翻译：混合检测装置
公开(公告)号：JP2003274945A
公开(公告)日：2003-09-30
申请号：JP2002087049
申请日：2002-03-26
申请人： Toshiba Corp , 株式会社東芝
发明人： YABE TOMOAKI , HASHIMOTO KOJI , ISHIUCHI HIDEMI , MIYAMOTO JUNICHI
IPC分类号： G01N33/53 , C12M1/00 , C12N15/00 , G01N27/12 , G01N27/327 , G01N27/416 , G01N37/00
摘要： PROBLEM TO BE SOLVED: To highly accurately detect a hybridization in a state compensating the changes of measurement environments. SOLUTION: This hybridization detection device comprises a probe electrode 11 to which a specimen DNA probe 12 is fixed, a reference electric current- generating means for generating at least one of an electric current I 1 equal to a probe electrode electric current, when the probe is hybridized with a specimen solution, and an electric current I 0 equal to a probe electrode current, when the probe is not hybridized with the specimen solution, and a detection means for detecting a probe electrode current I ta flowing in the probe electrode 11 exposed to the specimen solution and comparing the electric current I 1 with the electric current I 0 after subjected to electric current amplification treatments and electric current-voltage conversion treatments, thus determining the presence or absence of the hybridization on the probe electrode 11. COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：在补偿测量环境变化的状态下高精度地检测杂交。解决方案：该杂交检测装置包括固定样本DNA探针12的探针电极11，用于产生等电流I 1 中的至少一个的参考电流产生装置探针电极电流，当探针与试样溶液杂交，电流I 0 等于探针电极电流时，当探针与样品溶液不杂交时，用于检测在暴露于样品溶液的探针电极11中流动的探针电极电流I ta 的电流检测装置，并将电流I 1 与电流I 0 进行电流放大处理和电流 - 电压转换处理，从而确定在探针电极11上存在或不存在杂交。版权所有（C）2003，JPO

5. 发明专利

JP2003068985A Semiconductor memory chip and semiconductor memory 有权
标题翻译：半导体存储器芯片和半导体存储器
公开(公告)号：JP2003068985A
公开(公告)日：2003-03-07
申请号：JP2001260231
申请日：2001-08-29
申请人： Toshiba Corp , 株式会社東芝
发明人： YABE TOMOAKI , KAWASUMI ATSUSHI
IPC分类号： G11C11/41 , G11C5/00 , H01L21/82 , H01L21/822 , H01L23/50 , H01L27/04 , H01L27/10 , H01L27/11
CPC分类号： G11C5/025 , G11C5/063 , G11C11/413 , H01L23/50 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To enable a semiconductor memory chip having a flip connection structure to realize a high-speed operation by rectilinearly arranging signal wires that connect peripheral circuit units and sub-arrays to pass through between pads in pad arrangement areas so as to make the sub-arrays uniform in signal delay time and signals equal to one another in propagation time. SOLUTION: In a semiconductor memory chip having a flip connection structure, a memory cell array is divided into sub-arrays SA1,1 to SA16,16, the sub-arrays are arranged in trains, a peripheral circuit unit 11 and pad arrange regions 21 and 22 are arranged at an intermediate part of a sub-array arrangement, the pads Pd are arranged in the pad arrangement region at the same pitches as the sub-arrays, and signal wires S1,1 to S1,16 connecting the peripheral circuits units to the sub-arrays are rectilinearly arranged so as to pass through between the pads.
摘要翻译：要解决的问题：为了能够实现具有翻盖连接结构的半导体存储器芯片，通过直接布置连接外围电路单元和子阵列的信号线来实现高速操作，以在衬垫布置区域中的衬垫之间通过，以使在传播时间内，子阵列信号延迟时间和信号彼此相等。解决方案：在具有翻盖连接结构的半导体存储器芯片中，存储单元阵列被划分为子阵列SA1,1至SA16,16，子阵列布置成列，外围电路单元11和焊盘排列区域21 和22布置在子阵列布置的中间部分处，焊盘Pd以与子阵列相同的间距布置在焊盘布置区域中，并且连接外围电路单元的信号线S1,1至S1,16 子阵列被直线地布置成在垫之间穿过。

6. 发明专利

JP2008097787A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2008097787A
公开(公告)日：2008-04-24
申请号：JP2006281744
申请日：2006-10-16
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： TOHATA AKISHI , YABE TOMOAKI
IPC分类号： G11C11/417
CPC分类号： G11C7/14 , G11C7/22 , G11C7/227 , G11C11/413
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device in which activation timing of sense amplifiers included in cell arrays can be set for each cell array. SOLUTION: The semiconductor storage device includes: cell arrays 11-1, 11-2 in which a plurality of memory cells are arranged in row and column directions; bit lines GBL0, GBLK connected to the plurality of memory cells arranged in the column direction, respectively; local sense amplifiers 12-0, 12-K connected to the bit lines, respectively; first and second dummy cell arrays in which a plurality of dummy cells are arranged in the row and column directions; a dummy word line connected to the plurality of dummy cells arranged in the row direction; dummy local bit lines 16-1, 16-2 which are connected to the plurality of dummy cells arranged in the column directions and to which outputs from the dummy word lines are input; and local sense activation circuits 17-1, 17-2 activating the local sense amplifiers 12-0, 12-K in response to first and second control signals output from the dummy local bit lines. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以为每个单元阵列设置包括在单元阵列中的读出放大器的激活定时的半导体存储装置。解决方案：半导体存储装置包括：多个存储单元以行和列方向布置的单元阵列11-1,11-2; 分别连接到沿列方向布置的多个存储单元的位线GBL0，GBLK; 分别连接到位线的局部感测放大器12-0,12-K; 第一和第二虚拟单元阵列，其中多个虚设单元在行和列方向上排列; 连接到沿行方向布置的多个虚拟单元的虚拟字线; 虚拟本地位线16-1,16-2，其连接到布置在列方向上的多个虚拟单元，并且输入来自虚拟字线的输出; 以及局部感测激活电路17-1,17-2响应于从虚拟局部位线输出的第一和第二控制信号来激活本地读出放大器12-0,12-K。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2005004876A Semiconductor memory device and its evaluating method 审中-公开
标题翻译：半导体存储器件及其评估方法
公开(公告)号：JP2005004876A
公开(公告)日：2005-01-06
申请号：JP2003166852
申请日：2003-06-11
申请人： Toshiba Corp , 株式会社東芝
发明人： YABE TOMOAKI
IPC分类号： G01R31/28 , G06F11/10 , G11C29/12 , G11C29/42 , G11C29/00
CPC分类号： G06F11/1008 , G11C29/42 , G11C2029/1208 , G11C2029/3602
摘要： PROBLEM TO BE SOLVED: To shorten the test time and to reduce the test cost by performing simultaneously operation tests before correcting an error and after correcting the error.
SOLUTION: Write-in data is stored in a memory cell array 1, while test data required for correcting an error is generated for the write-in data and stored in a test data memory cell array 2. On the other hand, a syndrome signal is generated from the data read out from the memory cell array 1 and the test data read out from the test data memory cell array 2. And, an error of the read out data is corrected based on the syndrome signal and data after correcting the error is outputted to the outside. Also, simultaneously, an internal error I/O address signal specifying an address of an error bit of data before correcting an error is generated based on the syndrome signal and outputted to the outside.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：缩短测试时间并降低测试成本，通过在纠正错误和纠正错误之后执行同时操作测试。解决方案：写入数据存储在存储单元阵列1中，而为写入数据生成校正错误所需的测试数据并存储在测试数据存储单元阵列2中。另一方面，从从存储单元阵列1读出的数据和从测试数据存储单元阵列2读出的测试数据产生校正信号。并且，根据校正子信号和后面的数据校正读出数据的误差校正误差被输出到外部。此外，同时，基于该校正子信号产生指定校正错误之前的数据的错误位的地址的内部错误I / O地址信号并将其输出到外部。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2002373942A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2002373942A
公开(公告)日：2002-12-26
申请号：JP2002068176
申请日：2002-03-13
申请人： Toshiba Corp , 株式会社東芝
发明人： YABE TOMOAKI
IPC分类号： H01L27/04 , G05F1/56 , G11C11/407 , H01L21/822 , H03K19/00
摘要： PROBLEM TO BE SOLVED: To compensate for process variation for each chip, and to reduce a gate leak current.
SOLUTION: The semiconductor integrated circuit has a power step-down circuit and a group of MOS circuits. A power voltage is supplied to the power step-down circuit, and control is made by a standby control signal for indicating an operation or standby state. When the standby control signal indicates the operation state, a first internal power voltage being smaller than the power voltage is outputted to an internal power supply line. Contrarily, when the standby control signal indicates the standby state, a second internal power voltage smaller than the first one is outputted to the internal power supply line. The group of MOS circuits includes one MOS transistor or a plurality of MOS transistors operated by supplying the first or second internal power voltage.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了补偿每个芯片的工艺变化，并减少栅极泄漏电流。解决方案：半导体集成电路具有功率降压电路和一组MOS电路。电源电压被提供给功率降压电路，并且通过用于指示操作或待机状态的待机控制信号进行控制。当待机控制信号指示操作状态时，将小于电源电压的第一内部电源电压输出到内部电源线。相反，当待机控制信号指示待机状态时，小于第一内部电源电压的第二内部电力电压被输出到内部电源线。 MOS电路组包括通过提供第一或第二内部电源电压而工作的一个MOS晶体管或多个MOS晶体管。

9. 发明专利

JP2009099165A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2009099165A
公开(公告)日：2009-05-07
申请号：JP2007267132
申请日：2007-10-12
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： SUZUKI AZUMA , OTSUKA NOBUAKI , YABE TOMOAKI , HIRABAYASHI OSAMU , TOHATA AKISHI
IPC分类号： G11C29/04 , G11C11/413
摘要： PROBLEM TO BE SOLVED: To easily increase the number of redundancies in an SRAM, etc., by reducing area penalty in a similar way as a conventional dynamic column shift method.
SOLUTION: This semiconductor storage device includes a column shift redundancy circuit for dynamically shifting columns when an address input hits on a defective address. The redundancy column cell is divided into N pieces and column addresses different from each other are allocated to the divided cells.
COPYRIGHT: (C)2009,JPO&INPIT

10. 发明专利

JP2008102143A Hybridization detector 审中-公开
标题翻译：杂交检测器
公开(公告)号：JP2008102143A
公开(公告)日：2008-05-01
申请号：JP2007287780
申请日：2007-11-05
申请人： Toshiba Corp , 株式会社東芝
发明人： YABE TOMOAKI , HASHIMOTO KOJI , ISHIUCHI HIDEMI , MIYAMOTO JUNICHI
IPC分类号： G01N27/416 , C12M1/00 , C12Q1/68 , G01N27/327 , G01N27/414
摘要： PROBLEM TO BE SOLVED: To provide a hybridization detector operating precisely in a measurement environment fluctuation compensated condition. SOLUTION: This hybridization device includes a probe electrode 11 to which a specimen DNA probe is fixed. A current I 1 equal to a probe electrode current given when hybridization occurs between a probe and a specimen solution and a current I 0 equal to a probe electrode current given when no hybridization occurs between the probe and the specimen solution are generated, while a probe electrode current I ta flowing through the probe electrode 11 exposed to the specimen solution is detected, and the current I 0 and the current I 1 are compared with each other after current amplification and current/voltage conversion for determining presence/absence of hybridization on the probe electrode 11. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供在测量环境波动补偿条件下精确操作的杂交检测器。解决方案：该杂交装置包括固定标本DNA探针的探针电极11。电流I 1 等于在探针和样品溶液之间发生杂交时给出的探针电极电流和等于当没有杂交时给出的探针电极电流的电流I 0 ta ，并且检测电流I SB >和目前的I 1 在电流放大和电流/电压转换之间进行比较，以确定探针电极11上是否存在杂交。（C）2008，JPO＆INPIT

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