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1. 发明专利

JP2013117946A Memory card, host device and system 有权
标题翻译：存储卡，主机和系统
公开(公告)号：JP2013117946A
公开(公告)日：2013-06-13
申请号：JP2012222240
申请日：2012-10-04
申请人： Toshiba Corp , 株式会社東芝
发明人： NAGAI YUJI , SUZUKI TOSHIHIRO , SHIBATA NOBORU , KATO HIROSHI , MATSUSHITA TATSUYUKI
IPC分类号： G06F21/62 , G06F21/64 , H04L9/10
摘要： PROBLEM TO BE SOLVED: To prevent unauthorized use of confidential information.SOLUTION: A system includes a memory card and a host device communicable with the memory card. The memory card has a controller and a memory device controlled by the controller, storing secret data in an unreadable manner and encryption secret data in a readable manner. When receiving a command for reading the encryption secret data from the host device, the controller reads the encryption secret data from the memory device and transmits the encryption secret data to the host device. The memory device receives number data which was transmitted with a command for acquiring authentication information data from the host device, calculates the authentication information data by using the secret data. The host device verifies the authentication information data generated by the memory device.
摘要翻译：要解决的问题：防止未经授权使用机密信息。解决方案：系统包括存储卡和可与存储卡通信的主机设备。存储卡具有由控制器控制的控制器和存储器件，以可读方式存储秘密数据，并以可读方式存储加密秘密数据。当从主机装置接收到用于读取加密秘密数据的命令时，控制器从存储装置读取加密秘密数据，并将加密秘密数据发送到主机装置。存储装置接收用于从主机装置获取认证信息数据的命令发送的号码数据，通过使用秘密数据计算认证信息数据。主机设备验证存储设备生成的认证信息数据。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2013117884A Memory card, storage medium, and controller 有权
标题翻译：存储卡，存储媒体和控制器
公开(公告)号：JP2013117884A
公开(公告)日：2013-06-13
申请号：JP2011265306
申请日：2011-12-02
申请人： Toshiba Corp , 株式会社東芝
发明人： NAGAI YUJI , SUZUKI TOSHIHIRO , SHIBATA NOBORU , KATO HIROSHI , MATSUSHITA TATSUYUKI
IPC分类号： G06F21/74 , G11C16/02
CPC分类号： H04L9/0816 , G11B20/00086 , G11B20/00115 , G11B20/0021 , G11B2220/2516 , G11B2220/60 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device advantageous for preventing the unauthorized use of confidential information.SOLUTION: The semiconductor storage device includes: a cell array 11 having at least a normal area accessible from the outside and a confidential area having confidential information to which access from the outside is restricted and which is used for authentication recorded therein; an authentication circuit 17 for performing authentication with the outside; and a data cash 12 including a first data cash circuit accessible from the outside and a second data cash circuit to which the access from the outside is restricted. When receiving an authentication request including an authentication parameter from the outside, the semiconductor storage device stores the authentication parameter in the first data cash circuit, reads the confidential information from the confidential area, stores the read confidential information in the second data cash circuit, prohibits the output of the stored confidential information to the outside, encrypts the authentication parameter by the confidential information and acquires authentication information, and stores the authentication information in the first data cash circuit.
摘要翻译：要解决的问题：提供一种有利于防止未授权使用机密信息的半导体存储装置。解决方案：半导体存储装置包括：具有至少从外部可访问的正常区域的单元阵列11和具有来自外部的访问被限制并用于其中记录的认证的机密信息的机密区域; 用于与外部进行认证的认证电路17; 以及数据现金12，包括从外部可访问的第一数据现金电路和从外部进入的第二数据现金电路。半导体存储装置从外部接收到包含认证参数的认证请求时，将认证参数存储在第一数据现金电路中，从机密区域读取机密信息，将读取的机密信息存储在第二数据现金电路中，禁止将存储的机密信息输出到外部，通过机密信息加密认证参数，并获取认证信息，并将认证信息存储在第一数据现金电路中。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2012195515A Semiconductor device and manufacturing method for the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012195515A
公开(公告)日：2012-10-11
申请号：JP2011059821
申请日：2011-03-17
申请人： Toshiba Corp , 株式会社東芝
发明人： KUTSUKAKE HIROYUKI , ICHIGE MASAYUKI , KANDA KAZUE , SHIBATA NOBORU
IPC分类号： H01L27/115 , H01L21/336 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11529 , G11C11/5621 , G11C16/0483 , H01L21/823807 , H01L21/823892 , H01L27/11546
摘要： PROBLEM TO BE SOLVED: To provide a high-quality semiconductor device.SOLUTION: A semiconductor device comprises: a P-type semiconductor substrate 10; a Cell region including an N well 11 formed in the semiconductor substrate 10, a P well 12 formed in the semiconductor substrate 10 and on the N well 11, and a memory cell transistor MT formed on the P well 12; an HVP-Tr region including an N well 14 formed in the semiconductor substrate 10 and a transistor HVP-Tr formed on the N well 14; an HVN-Tr region including a transistor HVN-Tr formed on the semiconductor substrate 10; and an LVNE-Tr region including an N well 22 formed in the semiconductor substrate 10, a P well 23 formed in the semiconductor substrate 10 and on the N well 22, and a transistor LVNE-Tr formed on the P well 23. The positions of bottom planes of the N well 11 and the N well 22 are lower than the position of a bottom plane of the N well 14, and the position of the bottom plane of the N well 14 is lower than the positions of bottom planes of the P well 12 and the P well 23.
摘要翻译：要解决的问题：提供一种高质量的半导体器件。解决方案：半导体器件包括：P型半导体衬底10; 包括形成在半导体衬底10中的N阱11的单元区域，形成在半导体衬底10中的N阱11和形成在P阱12上的存储单元晶体管MT的P阱12; 包括形成在半导体衬底10中的N阱14和形成在N阱14上的晶体管HVP-Tr的HVP-Tr区; 包括形成在半导体衬底10上的晶体管HVN-Tr的HVN-Tr区; 以及包括形成在半导体衬底10中的N阱22，形成在半导体衬底10中的N阱22和N阱22上的P阱23以及形成在P阱23上的晶体管LVNE-Tr的LVNE-Tr区。 N阱11和N阱22的底面的面积比N阱14的底面的位置低，N阱14的底面的位置低于N阱14的底面的位置 P井12和P井23.版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2012138158A Semiconductor storage system 有权
标题翻译：半导体存储系统
公开(公告)号：JP2012138158A
公开(公告)日：2012-07-19
申请号：JP2010291304
申请日：2010-12-27
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIBATA NOBORU
IPC分类号： G11C16/06 , G11C16/02 , H01L21/336 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C5/147 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/30 , G11C2216/14
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage system which can suppress a peak current without providing a communication line for performing communications between a plurality of chips when the plurality of chips are mounted on the semiconductor storage system.SOLUTION: In the semiconductor storage system, power source wiring 81 is connected in common to a first semiconductor storage device 71a and a second semiconductor storage device 71b, and supplies a power source to the first and second semiconductor storage devices, voltage detection circuits 74a, 74b and 74c are provided on each of the first and second semiconductor storage devices, and detects a power source voltage of the power source wiring, and a control circuit 7 is provided on each of the first and second semiconductor storage devices, and prevents the operation of the first or second semiconductor storage device from shifting to next operation until the power source voltage is restored, when lowering of the power source voltage is detected by the voltage detection circuits.
摘要翻译：要解决的问题：提供一种半导体存储系统，其可以在多个芯片安装在半导体存储系统上时，不提供用于在多个芯片之间进行通信的通信线路而抑制峰值电流。解决方案：在半导体存储系统中，电源布线81共同连接到第一半导体存储装置71a和第二半导体存储装置71b，并将电源提供给第一和第二半导体存储装置，电压检测电路74a，74b和74c设置在第一和第二半导体存储装置中的每一个上，并检测电源布线的电源电压，并且控制电路7设置在第一和第二半导体存储装置中的每一个上，当通过电压检测电路检测到电源电压的降低时，防止第一或第二半导体存储装置的操作转移到下一个操作直到电源电压恢复。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2012048791A Multi-level nonvolatile semiconductor memory system 审中-公开
标题翻译：多级非线性半导体存储器系统
公开(公告)号：JP2012048791A
公开(公告)日：2012-03-08
申请号：JP2010191368
申请日：2010-08-27
申请人： Toshiba Corp , 株式会社東芝
发明人： KOBAYASHI NAOKI , HONMA MITSUYOSHI , SHIBATA NOBORU
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C11/5628
摘要： PROBLEM TO BE SOLVED: To shorten a data transfer time from a controller to a nonvolatile semiconductor memory.SOLUTION: A memory system includes: a nonvolatile semiconductor memory 1 having a plurality of memory cells for storing x bits(x is an integer of three or more) and provided with a memory cell array 11 in which bit allocation is performed to 2threshold distributions; and a controller 2 for controlling operation of the nonvolatile semiconductor memory 1 during writing. The controller 2 includes a data conversion circuit 22 for executing writing in first, second and third steps, generating 2(y is an integer, and y
摘要翻译：要解决的问题：缩短从控制器到非易失性半导体存储器的数据传送时间。存储系统包括：非易失性半导体存储器1，具有用于存储x位的多个存储单元（x为3以上的整数），并具有存储单元阵列11，在该存储单元阵列11中进行位分配， 2 x 阈值分布; 以及用于在写入期间控制非易失性半导体存储器1的操作的控制器2。控制器2包括用于在第一，第二和第三步骤中执行写入的数据转换电路22，在第一，第二和第三步骤中产生两个（SP）=“POST”> y （y是整数和y x 阈值分布，并产生用于产生2 y 阈值分布的ay位在第一步骤期间的x位的基础，并且在第一步骤期间将y位传送到非易失性半导体存储器1。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2011150781A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2011150781A
公开(公告)日：2011-08-04
申请号：JP2011049503
申请日：2011-03-07
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIBATA NOBORU , TANAKA TOMOHARU
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To improve data write speed by accelerating verifying operation. SOLUTION: A memory cell array 1 is configured to have a plurality of memory cells, each of the memory cells being connected to a word line and a bit line and storing one of n values (n is a natural number equal to or larger than 3). A control circuit 7 controls the potentials of the word line and bit line according to input data and writes the data into a memory cell. A data storage circuit 10 is connected to the bit line and stores data of at least 1 bit. When verifying whether the threshold voltage of the memory cell has reached a k-valued threshold voltage by the writing operation, the control circuit 7 performs the verifying operation with a threshold voltage lower than the k-valued threshold voltage. If the threshold voltage of the memory cell has exceeded the threshold voltage lower than the k-valued threshold voltage, the control circuit 7 sets the data within the data storage circuit to the same data to be written to an i-valued threshold voltage (i COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：通过加快验证操作来提高数据写入速度。解决方案：存储单元阵列1被配置为具有多个存储单元，每个存储器单元连接到字线和位线，并且存储n个值中的一个（n是等于或等于的自然数）大于3）。控制电路7根据输入数据控制字线和位线的电位，并将数据写入存储单元。数据存储电路10连接到位线并存储至少1位的数据。当通过写入操作来验证存储器单元的阈值电压是否达到k值阈值电压时，控制电路7以低于k值阈值电压的阈值电压执行验证操作。如果存储器单元的阈值电压已经超过低于k值阈值电压的阈值电压，则控制电路7将数据存储电路内的数据设置为相同的数据以写入i值的阈值电压（i

7. 发明专利

JP2011119025A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2011119025A
公开(公告)日：2011-06-16
申请号：JP2011061690
申请日：2011-03-18
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIBATA NOBORU
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To significantly reduce the number of parameters for generating a read voltage corresponding to a threshold level. SOLUTION: A semiconductor memory comprises a memory cell array and a control circuit. In the memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in matrix. The control circuit controls potentials of the word lines and the bit lines. In a reading operation for reading data from the memory cell, the control circuit starts non-selected word lines adjacent to a selected word line among the word lines, and thereafter starts the selected word line. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：显着减少用于产生对应于阈值水平的读取电压的参数的数量。解决方案：半导体存储器包括存储单元阵列和控制电路。在存储单元阵列中，连接到字线和位线的多个存储单元被排列成矩阵。控制电路控制字线和位线的电位。在从存储单元读取数据的读取操作中，控制电路在字线之间启动与选定字线相邻的未选择的字线，然后启动所选择的字线。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2011065736A Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：JP2011065736A
公开(公告)日：2011-03-31
申请号：JP2009217603
申请日：2009-09-18
申请人： Toshiba Corp , 株式会社東芝
发明人： FUTAYAMA TAKUYA , KONDO KATSUHISA , SHIBATA NOBORU
IPC分类号： G11C16/02
CPC分类号： G11C16/10 , G11C8/00 , G11C11/5621 , G11C16/0483 , G11C2211/5641
摘要： PROBLEM TO BE SOLVED: To secure an appropriate operation speed even when the memory capacity is increased farther and a multi-valent memory system is adopted. SOLUTION: A memory cell array 1 includes an area having first memory cells holding N bit data, and an area having second memory cells holding M bit (M is a natural number below N) data. Address data which the controller receives when accessing the first memory cells and address data which is received from outside when accessing the second memory cells are the same in their data structure. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：即使当存储器容量增加更多并且采用多价存储器系统时，即使确保适当的操作速度。解决方案：存储单元阵列1包括具有保持N位数据的第一存储单元的区域，以及具有保持M位（M为低于N）的第二存储单元的区域。访问第一存储器单元时控制器接收到的地址数据和在访问第二存储单元时从外部接收的地址数据在其数据结构中相同。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2011060423A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2011060423A
公开(公告)日：2011-03-24
申请号：JP2010288666
申请日：2010-12-24
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIBATA NOBORU , KANEBAKO KAZUNORI
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device for suppressing change in a threshold voltage of an erasing cell. SOLUTION: A plurality of memory cells each of which includes a NAND cell, are written from source line sides. By a first write operation, a threshold voltage of one memory cell among the plurality of memory cells is set to a first or second (first threshold COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于抑制擦除单元的阈值电压的变化的半导体存储器件。解决方案：从源极侧写入每个包括NAND单元的多个存储单元。通过第一写入操作，从多个存储单元中的一个存储单元的阈值电压从第一阈值被设置为第一或第二（第一阈值<第二阈值）阈值。通过第二写入操作，当一个存储单元的阈值电压处于第一阈值时，将阈值电压设置为第三阈值（第一阈值≤第三阈值）或第四阈值（第三阈值<第四阈值），并且当存储单元的阈值电压处于第二阈值，将阈值电压设定为第五阈值（第二阈值≤第五阈值）或第六阈值（第五阈值<第六阈值）。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2010003349A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2010003349A
公开(公告)日：2010-01-07
申请号：JP2008160691
申请日：2008-06-19
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIBATA NOBORU
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/10
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of reducing a breakdown voltage of a transistor by reducing a write-in voltage. SOLUTION: A memory cell array 1 connected to a word line and a bit line is constituted so that a plurality of memory cells for storing one value among n values (n is natural number of ≥2) are arranged in a matrix state. A control circuit 7 controls voltages of the word line and the bit line in accordance with input data and writes the data into the memory cells. By the control circuit 7, a first voltage is supplied to the word line of a selected cell at the write-in operation, and after a second voltage is supplied to at least one word line adjacent to the selected cell, the voltage of at least one word line adjacent to the selected cell is defined as a third voltage from the second voltage (second voltage COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供能够通过降低写入电压来降低晶体管的击穿电压的半导体存储装置。解决方案：连接到字线和位线的存储单元阵列1被构造成使得用于存储n个值（n是自然数≥2）中的一个值的多个存储单元被布置成矩阵状态。控制电路7根据输入数据控制字线和位线的电压，并将数据写入存储单元。通过控制电路7，在写入操作时将第一电压提供给所选择的单元的字线，并且在将至少一个与所选单元相邻的字线提供第二电压之后，至少将与所选单元相邻的一条字线定义为来自第二电压（第二电压<第三电压）的第三电压，并且将所选择的单元的字线的电压定义为来自第一电压的第四电压（第一电压 <第四电压）。版权所有（C）2010，JPO＆INPIT

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