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1. 发明专利

JP2013098274A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013098274A
公开(公告)日：2013-05-20
申请号：JP2011238311
申请日：2011-10-31
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA KEIICHI
IPC分类号： H01L27/095 , H01L21/3205 , H01L21/336 , H01L21/338 , H01L21/768 , H01L21/822 , H01L23/522 , H01L27/04 , H01L29/778 , H01L29/78 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that allows preventing the tendency of cracking of a semiconductor element and improving the formation yield of the element even if VIA holes are formed in high density.SOLUTION: A semiconductor device includes: a substrate 110; a gate electrode 124, a source electrode 120, and a drain electrode 122 that are disposed on a first surface of the substrate and each have a plurality of fingers; VIA holes SC that are disposed at under portions of each source electrode 120; and a ground electrode that is disposed on a second surface of the substrate opposite to the first surface and is connected to the source electrode through the VIA holes. The VIA holes SC are disposed along a different direction from a cleavage direction of a compound semiconductor crystal forming the substrate 110.
摘要翻译：要解决的问题：提供一种能够防止半导体元件的破裂倾向的半导体器件，并且即使高密度地形成VIA孔，也能够提高元件的形成量。解决方案：半导体器件包括：衬底110; 栅电极124，源电极120和漏电极122，其设置在基板的第一表面上，并且每个具有多个指状物; 设置在每个源电极120的下部的通孔SC; 以及接地电极，其设置在与所述第一表面相对的所述基板的第二表面上，并且通过所述VIA孔与所述源电极连接。 VIA孔SC沿着与形成衬底110的化合物半导体晶体的解理方向不同的方向设置。版权所有：（C）2013，JPO＆INPIT

2. 发明专利

JP2013004603A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2013004603A
公开(公告)日：2013-01-07
申请号：JP2011132125
申请日：2011-06-14
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA KEIICHI
IPC分类号： H01L21/338 , H01L21/205 , H01L21/28 , H01L29/417 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method capable of forming a gate electrode of a designed shape and size.SOLUTION: A semiconductor device manufacturing method according to a present embodiment comprises: forming laminates 17, 18 in which titanium layers 17a, 18a, aluminum layers 17b, 18b, nickel layers 17c, 18c and gold layers 17d, 18d are respectively laminated in this order on a surface of a semiconductor layer 12 at locations at a distance from each other; heating the laminates at a temperature higher than a melting point of aluminum to form a plurality of metal bodies 17', 18'; concurrently, forming ohmic contacts between the plurality of metal bodies 17', 18' and the semiconductor layer 12; subsequently, thinning the plurality of metal bodies 17', 18' to form a plurality of alloy layers 13a, 14a; forming a drain electrode 13 and a source electrode 14 respectively including the alloy layers 13a, 14a; subsequently, forming an opening 20 in a resist layer 19 between the drain electrode 13 and the source electrode 14; and forming a gate electrode 15 in the opening 20.
摘要翻译：要解决的问题：提供能够形成设计形状和尺寸的栅电极的半导体器件制造方法。解决方案：根据本实施例的半导体器件制造方法包括：其中钛层17a，18a，铝层17b，18b，镍层17c，18c和金层17d，18d分别层叠的层叠体17,18 依次在半导体层12的表面上彼此间隔一定距离; 在高于铝的熔点的温度下加热层压体以形成多个金属体17'，18'; 同时在多个金属体17'，18'和半导体层12之间形成欧姆接触; 随后，使多个金属体17'，18'变薄，形成多个合金层13a，14a; 形成分别包括合金层13a，14a的漏电极13和源电极14; 随后在漏电极13和源电极14之间的抗蚀剂层19中形成开口20; 并在开口20中形成栅电极15.版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2012114330A Power amplification device and coupled power amplification device 有权
标题翻译：功率放大器件和耦合功率放大器件
公开(公告)号：JP2012114330A
公开(公告)日：2012-06-14
申请号：JP2010263451
申请日：2010-11-26
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA KEIICHI
IPC分类号： H01L23/532 , H01L21/338 , H01L21/768 , H01L29/812
CPC分类号： H01L23/4824 , H01L23/4821 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an amplification device which reduces effects of inductance as much as possible by further shortening a distance from a source electrode to a via hole.SOLUTION: The power amplification device comprises: grounding parts connected to via holes for grounding; a source electrode grounding conductor which connects grounding parts; a source electrode coupled to the source electrode grounding conductor; an inner source electrode which is not in contact with the source electrode grounding conductor; a drain electrode; a gate electrode; and a grounding bridge directly connecting the inner source electrode and the grounding parts.
摘要翻译：要解决的问题：提供一种通过进一步缩短从源电极到通孔的距离尽可能地减小电感效应的放大装置。解决方案：功率放大装置包括：接地部分连接到通孔用于接地; 连接接地部件的源极接地导体; 源电极，其耦合到所述源电极接地导体; 不与源极接地导体接触的内部源电极; 漏电极; 栅电极; 以及直接连接内源电极和接地部的接地桥。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2006278721A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2006278721A
公开(公告)日：2006-10-12
申请号：JP2005095519
申请日：2005-03-29
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA KEIICHI
IPC分类号： H01L21/318 , H01L21/338 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which is capable of forming a protective insulating layer, without having to deteriorate the characteristics of a semiconductor device.
SOLUTION: When a silicon nitride (SiN) film is formed as a protective insulating layer by means of a parallel plate plasma CVD on the surface of a field effect transistor etc using gallium nitride; a parameter condition is formed, under which the emission intensity ratio (N391/SiN405) of the excited nitrogen molecule, having its emission peak at about the wavelength of 391 nm to the excited silicon nitride molecule, having its emission peak approximately at a wavelength of 405 nm is set at 0.5 or below is set intentionally so as to control the formation of the silicon nitride film.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够形成保护绝缘层的半导体器件制造方法，而不必劣化半导体器件的特性。解决方案：使用氮化镓在场效应晶体管等的表面上通过平行板等离子体CVD形成氮化硅（SiN）膜作为保护绝缘层; 形成参数条件，在该参数条件下，其激发的氮分子的发射强度比（N391 / SiN405）具有大约波长为391nm的激发态氮化硅分子的发射峰，其发射峰大约在波长 405nm设定为0.5以下，有意地设定，以便控制氮化硅膜的形成。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2011060946A Semiconductor device having position displacement inspection pattern and pattern position displacement inspection method 审中-公开
标题翻译：具有位置偏移检测模式和模式位移检测方法的半导体器件
公开(公告)号：JP2011060946A
公开(公告)日：2011-03-24
申请号：JP2009208075
申请日：2009-09-09
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA KEIICHI
IPC分类号： H01L21/66 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide a means which has a position displacement inspection pattern to improve the accuracy of pattern position displacement inspection.
SOLUTION: A semiconductor device is provided with a plurality of FETs, a plurality of pairs of reference inspection patterns 19 which are formed simultaneously with drain electrodes and source electrodes of the FETs in a region around an element formation region and provided at regular intervals, respectively, a plurality of inspection target inspection patterns 20 which are formed simultaneously with gate electrodes of the FETs and provided at intervals different from the intervals of the reference inspection patterns 19 between a plurality of pairs of the reference inspection patterns 19, a metal resistive layer 18 which is formed so as to be in contact with the plurality of inspection target inspection patterns 20 and the plurality of pairs of reference inspection patterns 19, a means which measures first resistance between the inspection target inspection patterns 20 and the reference inspection pattern 19 which are adjacent to one-end sides of the patterns 20, and second resistance between the inspection target inspection patterns 20 and the reference inspection patterns 19 which are adjacent to other sides of the patterns 20.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供具有位置检查图案的装置，以提高图案位置位移检查的精度。解决方案：半导体器件设置有多个FET，多对参考检查图案19，其在元件形成区域周围的区域中与漏极电极和源电极同时形成并且设置在规则间隔分别与多个检查对象检查图案20形成，这些检查对象检查图案20与FET的栅电极同时形成，并且以与参考检查图案19的间隔不同的间隔设置在多对参考检查图案19之间，金属形成为与多个检查对象检查图案20和多对基准检查图案19接触的电阻层18，测量检查对象检查图案20与基准检查图案之间的第一电阻的装置 19，其与图案20的一端侧相邻，第二抗蚀剂检查对象检查图案20与与图案20的其他侧面相邻的基准检查图案19之间的距离。（C）2011，JPO＆INPIT

6. 发明专利

JP2009176929A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009176929A
公开(公告)日：2009-08-06
申请号：JP2008013720
申请日：2008-01-24
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA KEIICHI
IPC分类号： H01L21/338 , H01L21/205 , H01L29/778 , H01L29/812
CPC分类号： H01L29/1029 , H01L29/2003 , H01L29/207 , H01L29/7785
摘要： PROBLEM TO BE SOLVED: To improve high frequency characteristics for stable high frequency performance, by reducing leak current and current collapse by deactivating piezoelectric charge to obtain a semiconductor layer of high resistance.
SOLUTION: A semiconductor device comprises a substrate 10, a nitride compound semiconductor layer 14 which, having been doped with a first transition metal atom, is arranged on the substrate, an aluminum nitride gallium layer (Al
x Ga
1-x N)(0.1≤x≤1)16 arranged on the nitride compound semiconductor layer 14, a nitride compound semiconductor layer 18 which, having been doped with a second transition metal atom, is arranged on the aluminum nitride gallium layer (Al
x Ga
1-x N)(0.1≤x≤1)16, an aluminum nitride gallium layer (Al
y Ga
1-y N)(0.1≤y≤1)22 arranged on the nitride compound semiconductor layer 18 having been doped with the second transition metal atom, and a gate electrode 26, source electrode 24, and drain electrode 28 arranged on the aluminum nitride gallium layer (Al
y Ga
1-y N)(0.1≤y≤1)22.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提高稳定的高频性能的高频特性，通过减少泄漏电流和通过使压电电荷失活来获得电流崩溃以获得高电阻的半导体层。解决方案：半导体器件包括衬底10，已经掺杂有第一过渡金属原子的氮化物化合物半导体层14被布置在衬底上，氮化铝镓层（Al x < 设置在氮化物半导体层14上的SB> Ga 1-x （0.1≤x≤1）16，掺杂有第二过渡金属原子的氮化物半导体层18，设置在氮化铝镓层（Al xSH 1-x≤N）（0.1≤x≤1）16上，氮化铝镓层（Al 配置在已经掺杂有第二过渡金属原子的氮化物半导体层18上的Ga（S）1-y N）（0.1≤y≤1）22，以及栅电极26，源电极24和布置在氮化铝镓层上的漏电极28（0.1≤y≤1）22（Al≤S≤1≤y≤1）22。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2007043037A Substrate for semiconductor layer deposition, field effect semiconductor device, and manufacturing method thereof 有权
标题翻译：用于半导体层沉积的衬底，场效应半导体器件及其制造方法
公开(公告)号：JP2007043037A
公开(公告)日：2007-02-15
申请号：JP2005266939
申请日：2005-09-14
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA KEIICHI
IPC分类号： H01L21/338 , H01L21/02 , H01L21/20 , H01L21/205 , H01L29/812
CPC分类号： H01L21/02378 , H01L21/0242 , H01L21/0243 , H01L21/0254 , H01L21/02609 , H01L29/045 , H01L29/2003 , H01L29/66462 , H01L29/7787
摘要： PROBLEM TO BE SOLVED: To improve a reliability and yield of semiconductor device formed, and obtain a substrate for semiconductor layer deposition making its forming process efficient. SOLUTION: A plurality of linear protrusions 3 are formed along a direction of cleavage plane of deposited gallium nitride (GaN) on a silicon on sapphire 2 used as a base. When a gallium nitride (GaN) layer 5 is deposited, a crack 6 is positively generated in the gallium nitride (GaN) layer 5 by concentrating a stress occurring within the layer to a portion locating an upper layer of the linear protrusions 3. A mark 4 for location detection is arranged on the silicon on sapphire 2, then a detection of forming location of element with an exposure device is made to be easy, and its arranging location locates between the plurality of the protrusions 3 simultaneously, then it is made to correspond to the portion of stable gallium nitride (GaN) layer 5 in which the occurrence of irregular cracks is prevented. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提高形成的半导体器件的可靠性和产率，并获得用于半导体层沉积的衬底，使其成型工艺有效。解决方案：在用作基底的蓝宝石2上的硅上沿着沉积的氮化镓（GaN）的解理面的方向形成多个线状突起3。当沉积氮化镓（GaN）层5时，通过将发生在层内的应力集中到定位直线突起3的上层的部分，在氮化镓（GaN）层5中积极地产生裂纹6.标记用于位置检测的位置检测装置4布置在蓝宝石2上的硅上，然后使用曝光装置检测元件的形成位置是容易的，并且其布置位置同时位于多个突起3之间，然后制成对应于其中防止发生不规则裂纹的稳定氮化镓（GaN）层5的部分。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2015053456A 半導体装置及びその製造方法有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2015053456A
公开(公告)日：2015-03-19
申请号：JP2013186732
申请日：2013-09-09
申请人：株式会社東芝 , Toshiba Corp
发明人： MATSUSHITA KEIICHI , SASAKI HARUKA
IPC分类号： H01L21/52 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/522
CPC分类号： H01L23/3736 , H01L21/50 , H01L23/10 , H01L23/142 , H01L23/4827 , H01L24/03 , H01L24/05 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/83 , H01L2224/0346 , H01L2224/04026 , H01L2224/05073 , H01L2224/05082 , H01L2224/05083 , H01L2224/05144 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05647 , H01L2224/2741 , H01L2224/2743 , H01L2224/29082 , H01L2224/29083 , H01L2224/29084 , H01L2224/29111 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29164 , H01L2224/29166 , H01L2224/29169 , H01L2224/32245 , H01L2224/32501 , H01L2224/48091 , H01L2224/73265 , H01L2224/83192 , H01L2224/83193 , H01L2224/83203 , H01L2224/83359 , H01L2224/83379 , H01L2224/83447 , H01L2224/83825 , H01L2224/85444 , H01L2924/00014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/13064 , H01L2924/13091 , H01L2924/161 , H01L2924/16195 , H01L2924/163 , H01L2924/171 , H01L2924/2064 , H01L2224/05644 , H01L2924/00012 , H01L2224/06164 , H01L2224/45099
摘要：【課題】高放熱性で高生産性の半導体装置及びその製造方法を提供する。【解決手段】実施形態によれば、半導体素子と、Cuを含む実装部材と、半導体素子と実装部材との間に設けられた接合層と、を含む半導体装置が提供される。接合金層は、TiとCuとを含む第1領域と、第1領域と実装部材との間に設けられSnとCuとを含む第2領域と、を含む。第1領域におけるTiの組成比は、半導体素子から実装部材に向かう第1方向に沿って減少する。第2領域におけるSnの組成比は、第1方向とは反対の第2方向に沿って減少する。第1領域におけるTiの組成比が、第1領域における最大値の0.1倍となる第1位置は、第2領域におけるSnの組成比が最大値の0.1倍となる第2位置と、半導体素子と、の間に位置する。第1位置と第2位置との間の距離は、0.1μm以上である。【選択図】図1
摘要翻译：要解决的问题：提供具有高散热性和高生产率的半导体器件; 并提供半导体器件的制造方法。解决方案：根据实施例的半导体器件包括：半导体元件; 含Cu的安装部件; 以及设置在所述半导体元件和所述安装部件之间的接合金属层。接合金属层包括含有Ti和Cu的第一区域和设置在第一区域和安装部件之间并且包含Sn和Cu的第二区域。第一区域中的Ti组成比沿半导体元件朝向安装部件的第一方向减小。第二区域中的Sn组成区域在与第一方向相反的第二方向上减小。第一区域中的Ti组成比为第一区域中的最大值的0.1倍的第一位置位于半导体元件与第二区域中的Sn组成比为最大值的0.1倍的第二位置第二区。第一位置和第二位置之间的距离为0.1μm及以上。

9. 发明专利

JP2010161110A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010161110A
公开(公告)日：2010-07-22
申请号：JP2009000865
申请日：2009-01-06
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA KEIICHI
IPC分类号： H01L21/338 , H01L21/28 , H01L29/417 , H01L29/423 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a high performance semiconductor device which disperses generated heat by preventing concentration of power density and reduces electric phase difference.
SOLUTION: The semiconductor device includes a nitride-based compound semiconductor layer arranged on a substrate, an active region arranged on the nitride-based compound semiconductor layer and consisting of an aluminum nitride gallium layer (Al
x Ga
1-x N) (0.1≤x≤1), an element isolation region which isolates the active regions from each other, a gate electrode 24, a source electrode 20 and a drain electrode 22 arranged on the active regions surrounded by the element isolation region, and a gate terminal electrode 240, a source terminal electrode 200 and a drain terminal electrode 220 arranged on the element isolation region 14 and connected, respectively, with the gate electrode 24, the source electrode 20 and the drain electrode 22, wherein the branch of the gate electrode 24 is constituted of fractal figure of recursive self-similarity.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过防止功率密度的集中和减小电相差而分散发热的高性能半导体器件。解决方案：半导体器件包括布置在衬底上的氮化物基化合物半导体层，布置在氮化物基化合物半导体层上的有源区，由氮化铝镓层（Al x

10. 发明专利

JP2010062321A Semiconductor device and fabrication method for the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010062321A
公开(公告)日：2010-03-18
申请号：JP2008226248
申请日：2008-09-03
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA KEIICHI
IPC分类号： H01L21/338 , H01L21/76 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which is highly reliable, and has high performance and high power, and to provide a fabrication method for the semiconductor device.
SOLUTION: The semiconductor device includes a substrate 10, a nitride based compound semiconductor layer 12 placed on the substrate 10; an active area which is placed on the nitride based compound semiconductor layer 12, and is composed of an aluminum gallium nitride layer (Al
x Ga
1-x N where 0.1≤x≤1) 14; an element isolation region 24 which performs isolation of the active area mutually; a gate electrode 20, a source electrode 18, and a drain electrode 26 which have been placed on the active area surrounded by the isolation region 24; and groove portions 28a and 28b formed by etching for a part under the gate electrode 20.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供高可靠性，高性能和高功率的半导体器件，并提供半导体器件的制造方法。解决方案：半导体器件包括衬底10，放置在衬底10上的基于氮化物的化合物半导体层12; 放置在氮化物基化合物半导体层12上的有源区，由氮化镓铝层（Al x Ga 1-x N组成，其中0.1≤x ≤1）14; 元件隔离区域24，其相互地执行有源区域的隔离; 已经被放置在由隔离区域24包围的有源区域上的栅电极20，源电极18和漏电极26; 以及通过蚀刻用于栅电极20下方的部分形成的凹槽部分28a和28b。版权所有（C）2010，JPO＆INPIT

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