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1. 发明专利

JP2011035268A Semiconductor memory device, and method of manufacturing the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2011035268A
公开(公告)日：2011-02-17
申请号：JP2009181798
申请日：2009-08-04
申请人： Toshiba Corp , 株式会社東芝
发明人： KONDO MASAKI , ISOBE KAZUAKI
IPC分类号： H01L29/792 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device that increases the coupling ratio of a control gate to a floating gate without increasing a chip size, and to provide a method of manufacturing the same.
SOLUTION: The semiconductor memory device includes: a plurality of active areas formed on the surface of a semiconductor substrate; an element isolation part provided between the adjacent active areas; a tunnel insulating film provided on the active areas; a floating gate including a lower gate part which is opposed to each active area through the tunnel insulating film and an upper gate part having a width larger than that of the lower gate part and provided on the lower gate part; an intermediate insulating film provided on the upper surface and the side face of the floating gate; and a control gate provided on the upper surface and the side face of the floating gate through the intermediate insulating film. The lower end of the control gate is closer to the semiconductor substrate than the boundary between the upper gate part and the lower gate part.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种在不增加芯片尺寸的情况下增加控制栅极与浮动栅极的耦合比的半导体存储器件，并提供其制造方法。解决方案：半导体存储器件包括：形成在半导体衬底的表面上的多个有源区; 元件隔离部分，设置在相邻的有效区域之间; 设置在活动区域上的隧道绝缘膜; 包括通过隧道绝缘膜与每个有源区相对的下栅极部的浮栅，以及设置在下栅极部上的宽度大于下栅极部的宽度的上栅极部; 设置在所述浮动栅极的上表面和所述侧面上的中间绝缘膜; 以及通过中间绝缘膜设置在浮置栅极的上表面和侧面上的控制栅极。控制栅极的下端比上部栅极部分和下部栅极部分之间的边界更靠近半导体衬底。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2007294750A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007294750A
公开(公告)日：2007-11-08
申请号：JP2006122391
申请日：2006-04-26
申请人： Toshiba Corp , 株式会社東芝
发明人： ISOBE KAZUAKI
IPC分类号： H01L21/8247 , H01L21/3205 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11536
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which suppresses the variation of the characteristics due to the shape of an active region.
SOLUTION: The semiconductor device comprises element isolations 20 at least a part of which is provided in the semiconductor substrate for sectioning active regions on a semiconductor substrate, memory cell transistors, and selective transistors provided on the active regions. The memory cell transistor is sectioned by a slit 26 provided so as to include at least a part of the active region, and comprises a first gate electrode 24 provided on a channel region through a gate insulation film 22, and a second gate electrode 32 provided through an inter-electrode insulation film 28, covering the first gate electrode 24. The selective transistor is provided on the active region through the gate insulation film 22 and comprises a third gate electrode 24S connected to a wiring, and a fourth gate electrode 32 formed on the third gate electrode 24S through the insulation film 28.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供抑制由于活性区域的形状引起的特性变化的半导体器件。解决方案：半导体器件包括元件隔离件20，其至少一部分设置在半导体衬底中，用于在半导体衬底上划分有源区域，存储单元晶体管以及设置在有源区域上的选择性晶体管。存储单元晶体管被设置成包括有源区的至少一部分的狭缝26分割，并且包括设置在通过栅极绝缘膜22的沟道区上的第一栅电极24和设置在栅极绝缘膜22上的第二栅电极32 通过覆盖第一栅电极24的电极间绝缘膜28.选择晶体管通过栅极绝缘膜22设置在有源区上，并且包括连接到布线的第三栅电极24S和形成的第四栅电极32 通过绝缘膜28在第三栅电极24S上。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2007012779A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007012779A
公开(公告)日：2007-01-18
申请号：JP2005189950
申请日：2005-06-29
申请人： Toshiba Corp , 株式会社東芝
发明人： CHORI KANJI , ISOBE KAZUAKI
IPC分类号： H01L21/8234 , H01L21/28 , H01L27/088 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To prevent the lowering of breakdown voltage of a high breakdown voltage system MOS transistor accompanying a thin film of a gate electrode for miniaturization in a semiconductor integrated circuit device, where a logic system MOS transistor and the high breakdown voltage system MOS transistor are mixed-loaded on the same substrate.
SOLUTION: The high breakdown voltage system MOS transistor 31 has a thick film gate electrode 33 thicker than a thin film gate electrode 23 of a logic system MOS transistor 21, for example. There is provided a thick film gate side wall insulating film 34 having a side wall length in response to the film thickness of the thick film gate electrode 33 on a side wall of the thick film gate electrode 33. Further, the high withstand voltage system MOS transistor 31 has an LDD structure 35 having an LDD length in response to the side wall length of the thick film gate side wall insulating film 34.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了防止伴随着半导体集成电路器件中的用于小型化的栅电极的薄膜的高击穿电压系统MOS晶体管的击穿电压降低，其中逻辑系统MOS晶体管和高击穿电压系统MOS晶体管被混合在同一衬底上。解决方案：高耐压系统MOS晶体管31例如具有比逻辑系统MOS晶体管21的薄膜栅电极23厚的厚膜栅电极33。根据厚膜栅电极33的侧壁上的厚膜栅极33的膜厚，设置有具有侧壁长度的厚膜栅侧壁绝缘膜34.此外，高耐压系统MOS 晶体管31具有响应于厚膜栅极侧壁绝缘膜34的侧壁长度具有LDD长度的LDD结构35。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2009117778A Semiconductor storage apparatus and method of manufacturing the same 审中-公开
标题翻译：半导体存储装置及其制造方法
公开(公告)号：JP2009117778A
公开(公告)日：2009-05-28
申请号：JP2007292422
申请日：2007-11-09
申请人： Toshiba Corp , 株式会社東芝
发明人： ISOBE KAZUAKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage apparatus, having the distance between control gate layers of a memory cell transistor and that between control gate layers of a selecting transistor for carrying out high integration of memory cells made fully small, and to provide a method of manufacturing the same.
SOLUTION: A plurality of memory cells are arranged so that two electric charge storing layers 15 and two gate layers 19 are arranged alternately in line, in a first direction parallel to the surface of a semiconductor substrate. A diffusion layer 24 of a selecting transistor is extended, in a second direction which is parallel to the surface of the semiconductor substrate and crosses the first direction to configure a source line. A diffusion layer 22 of a memory cell transistor is extended in the second direction, parallel to the surface of the semiconductor substrate to configure a bit line. A control gate layer 17 of the memory cell transistor is formed on the two electric charge storing layers 15, adjacent to each other in the first direction via an insulating film between gates.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储装置，其具有存储单元晶体管的控制栅极层与选择晶体管的控制栅极层之间的距离，用于实现非常小的存储单元的高集成度;以及以提供其制造方法。解决方案：多个存储单元布置成使得两个电荷存储层15和两个栅极层19在平行于半导体衬底的表面的第一方向上交替排列布置。选择晶体管的扩散层24在与半导体衬底的表面平行的第二方向上延伸并与第一方向交叉以构成源极线。存储单元晶体管的扩散层22在第二方向上延伸，平行于半导体衬底的表面以配置位线。存储单元晶体管的控制栅极层17经由栅极之间的绝缘膜在第一方向上彼此相邻地形成在两个电荷存储层15上。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2005129568A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005129568A
公开(公告)日：2005-05-19
申请号：JP2003360727
申请日：2003-10-21
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWASAKI HIROHISA , ISOBE KAZUAKI
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/8244 , H01L23/52 , H01L27/11 , H01L29/417 , H01L29/76
CPC分类号： H01L27/11 , H01L27/1104
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of shrinking spaces among patterns and a manufacturing method for the semiconductor device.
SOLUTION: The semiconductor device has a first wiring layer 14a with a first lower end 17b, and a first upper end 17a projected from the first lower end 17b; and a second lower end 18b and a second upper end 18a projected from the second lower end section 18b. The second upper end 18a is faced at a first interval X to the first upper end 17a, and the second lower end 18b has the first lower end 17b, and a second wiring layer 14b faced at a second interval Y larger than the first interval X to the first lower end 17b.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够收缩图案间的空间的半导体器件和半导体器件的制造方法。解决方案：半导体器件具有第一布线层14a，第一布线层14a具有第一下端17b，第一上端17a从第一下端17b突出; 以及从第二下端部18b突出的第二下端18b和第二上端18a。第二上端部18a以第一间隔X面对第一上端部17a，第二下端部18b具有第一下端部17b，第二配线层14b面对大于第一间隔X的第二间隔Y 到第一下端17b。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2003031770A Semiconductor memory device and its manufacturing method 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2003031770A
公开(公告)日：2003-01-31
申请号：JP2001220189
申请日：2001-07-19
申请人： Toshiba Corp , 株式会社東芝
发明人： ISOBE KAZUAKI
IPC分类号： H01L21/8238 , H01L21/8247 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11531
摘要： PROBLEM TO BE SOLVED: To solve the problem that, when an N-type impurity is implanted by using a mask for forming a gate pattern of a cell transistor to reduce manufacturing steps of a semiconductor memory device, the N-type impurity is also implanted in a region for forming a P-type contact so that a sufficient impurity concentration cannot be obtained to take a contact.
SOLUTION: A method for manufacturing the semiconductor memory device comprises a step of forming a silicon oxide film 4a for isolating a cell region from a peripheral region in a P-well 3 on a surface of a semiconductor substrate 1. Thus, the method further comprises the steps of coating the peripheral region, forming a gate electrode 9 of the cell transistor 7 by using a photoresist having a gate pattern of the cell region, and ion implanting the photoresist by using as it is. Then, since the region formed of a P-type impurity diffused layer 6 is covered with the photoresist, the N-type impurity is not implanted, a photolithographic step can be reduced, and the impurity concentration of the layer 6 sufficient to take the contact is obtained.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题为了解决通过使用用于形成单元晶体管的栅极图案的掩模注入N型杂质以减少半导体存储器件的制造步骤的问题，也将N型杂质植入在用于形成P型接触的区域中，使得不能获得足够的杂质浓度进行接触。解决方案：一种用于制造半导体存储器件的方法包括在半导体衬底1的表面上形成用于将单元区域与P阱3中的周边区域隔离的氧化硅膜4a的步骤。因此，该方法还包括通过使用具有单元区域的栅极图案的光致抗蚀剂形成外围区域的步骤，通过使用具有栅极图案的光致抗蚀剂形成单元晶体管7的栅电极9，以及通过使用原样离子注入光致抗蚀剂。然后，由于由P型杂质扩散层6形成的区域被光致抗蚀剂覆盖，所以不注入N型杂质，可以降低光刻步骤，并且层6的杂质浓度足以进行接触获得。

7. 发明专利

JP2009081202A Semiconductor memory device and its manufacturing method 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2009081202A
公开(公告)日：2009-04-16
申请号：JP2007248021
申请日：2007-09-25
申请人： Toshiba Corp , 株式会社東芝
发明人： ISOBE KAZUAKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/0207 , H01L27/11519 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To control GIDL in a flash EEPROM constituted of a memory cell transistor and a selection transistor. SOLUTION: A plurality of memory cells comprising a memory cell transistor CT which has a gate electrode 12 of a laminate structure comprising a charge storage layer 15 and a control gate layer 17 and a selection transistor ST which shares one of source and drain diffusion layers with the memory cell transistor CT are arranged on a semiconductor substrate. The impurity concentration of the source or drain diffusion layer 21 shared by the memory cell transistor CT and the selection transistor ST in each of the plurality of memory cells is set to be lower than those of the other source and drain diffusion layers 22a and 23a in each memory cell. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：控制由存储单元晶体管和选择晶体管构成的闪速EEPROM中的GIDL。解决方案：包括具有包括电荷存储层15和控制栅极层17的层叠结构的栅电极12的存储单元晶体管CT的多个存储单元以及共享源极和漏极之一的选择晶体管ST 具有存储单元晶体管CT的扩散层布置在半导体衬底上。由多个存储单元中的每一个存储单元晶体管CT和选择晶体管ST共享的源极或漏极扩散层21的杂质浓度被设定为低于其他源极和漏极扩散层22a和23a的杂质浓度每个存储单元。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2007184367A Non-volatile semiconductor storage device 审中-公开
标题翻译：非挥发性半导体存储器件
公开(公告)号：JP2007184367A
公开(公告)日：2007-07-19
申请号：JP2006000748
申请日：2006-01-05
申请人： Toshiba Corp , 株式会社東芝
发明人： KITAMURA SHOTA , ISOBE KAZUAKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To reduce the size of a memory cell array, without depending upon the presence of the generation of cavities, even if the spacing distances are shortened to the extent that the cavities are generated in embedding materials, when interlayer films are embedded in the spacings of the memory cell array in a NOR flash memory, having a 2-transistor structure.
SOLUTION: The NOR flash memory, having the 2 transistor structure, has a plurality of drain contacts DC intermittently disposed in the row direction on drain regions D held in common by mutual cell transistors CT, and brought into contact with each drain region, respectively; and a plurality of bit lines BL, fitted in response to each row of the cell transistors on the cell array and composed of metallic wirings disposed in the row direction, so as to be brought into contact with a plurality of the drain contacts in the same row in common, respectively. The NOR flash memory further has a plurality of local source lines LS brought into contact, in response to the upper sections of a plurality of lines of source regions S held in common by mutual selector gate transistors ST, and comprising conductive substances arranged in the line direction, astride over element isolation regions 16 among rows.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了减小存储单元阵列的尺寸，不依赖于存在空腔的产生，即使间隔距离缩短到在嵌入材料中产生腔的程度，当中间层具有2晶体管结构的NOR闪速存储器中的薄膜嵌入在存储单元阵列的间隔中。解决方案：具有2晶体管结构的NOR闪速存储器具有多个漏极接触DC，这些漏极接触DC在行方向上间隔地设置在由共用单元晶体管CT共同保持的漏极区域D上，并与每个漏极区域接触，分别; 以及多个位线BL，其响应于单元阵列上的每行单元晶体管而被配合，并且由沿行方向布置的金属布线组成，以便与其相同的多个漏极触点接触行共同点。 NOR闪存进一步具有响应于由互选择栅极晶体管ST共同保持的多个源极区域S的上部部分而接触的多个本地源极线LS，并且包括布置在该线中的导电物质方向，跨越行中的元件隔离区域16。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2011171582A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2011171582A
公开(公告)日：2011-09-01
申请号：JP2010035028
申请日：2010-02-19
申请人： Toshiba Corp , 株式会社東芝
发明人： KASAI TAKAMICHI , UMEZAWA AKIRA , ISOBE KAZUAKI , HIRATA YOSHIHARU
IPC分类号： H01L21/8247 , G11C16/02 , G11C16/06 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/30 , G11C16/0483 , G11C16/08
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which controls disturbance at writing/erasing and suppresses an increase in area. SOLUTION: The nonvolatile semiconductor memory device includes a first well region of a first conductivity type in which a first cell array 32 containing a plurality of memory cells MC has been formed, a second well region of a first conductivity type in which a second cell array 32 containing a plurality of memory cells MC has been formed, and a third well region of a second conductivity type containing the first and second well regions, and further includes a bit line BL commonly connected to a memory cell which the first cell array 32 contains and a memory cell which the second cell array 32 contains and a column decoder 13 connected to the bit line BL. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种控制写入/擦除干扰的非易失性半导体存储器件，并抑制面积的增加。解决方案：非易失性半导体存储器件包括第一导电类型的第一阱区，其中形成有多个存储单元MC的第一单元阵列32，第一导电类型的第二阱区，其中已经形成了包含多个存储单元MC的第二单元阵列32和包含第一和第二阱区的第二导电类型的第三阱区，并且还包括共同连接到存储单元的位线BL，第一单元阵列32包含第二单元阵列32所包含的存储单元和连接到位线BL的列解码器13。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2010165788A Nonvolatile semiconductor memory 审中-公开
标题翻译：非易失性半导体存储器
公开(公告)号：JP2010165788A
公开(公告)日：2010-07-29
申请号：JP2009005851
申请日：2009-01-14
申请人： Toshiba Corp , 株式会社東芝
发明人： ISOBE KAZUAKI , TANAKA MASASHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory in which a memory cell is constituted with a memory cell transistor and a select transistor and which requires no source contact.
SOLUTION: This nonvolatile memory includes: a memory cell transistor containing a charge accumulating layer 15 provided through a silicon oxide film, an intergate insulating film, a control gate electrode 17, and a drain diffusion region 25; a select transistor provided adjacent to the memory cell transistor containing a select gate electrode 18 provided through a silicon oxide film, an intergate insulating film, a gate electrode 19, and a source/drain diffusion region 26 shared by the memory cell transistor also as a source/drain diffusion region 26 of the memory cell transistor; a source-line formed by extending a source diffusion region 27 of the select transistor in a semiconductor substrate; and a bit-line 29 electrically connected with the drain diffusion region 25 of the memory cell transistor.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供其中存储单元由存储单元晶体管和选择晶体管构成并且不需要源极接触的非易失性存储器。该非易失性存储器包括：存储单元晶体管，其含有通过氧化硅膜提供的电荷累积层15，栅极间绝缘膜，控制栅电极17和漏扩散区25; 设置在与存储单元晶体管相邻的存储单元晶体管附近设置的选择晶体管，其包含通过氧化硅膜提供的选择栅极电极18，栅极绝缘膜，栅极电极19和由存储单元晶体管共享的源极/漏极扩散区域26，存储单元晶体管的源/漏扩散区26; 通过在半导体衬底中延伸选择晶体管的源极扩散区域27形成的源极线; 以及与存储单元晶体管的漏极扩散区域25电连接的位线29。版权所有（C）2010，JPO＆INPIT

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