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1. 发明授权

US06510496B1 Shared memory multiprocessor system and method with address translation between partitions and resetting of nodes included in other partitions 失效
标题翻译：共享内存多处理器系统和分区之间的地址转换和其他分区中包含的节点的重置的方法
公开(公告)号：US06510496B1
公开(公告)日：2003-01-21
申请号：US09501978
申请日：2000-02-11
申请人： Toshiaki Tarui , Toshio Okochi , Shinichi Kawamoto
发明人： Toshiaki Tarui , Toshio Okochi , Shinichi Kawamoto
IPC分类号： G06F1210
CPC分类号： G06F12/0284 , G06F12/0831 , G06F12/1072 , G06F2212/656
摘要： A symmetric multiprocessor (SMP) of hierarchical connection realizing an inter-partition shared memory has at the gateway of an inter-node connection switch from each node, a translator for translating an address of an access command for an area shared between partitions, between a real address used in a partition and a shared area address used in common between partitions. Thereby, the address of a local area of each partition is freely set, and cache coherent control of a shared area is conducted at high speed by using a snoop command of the hierarchical connection SMP. Fault containment between partitions is realized by checking conformity between the address of the access command issued from another partition and the shared area configuration. Nodes included in other partitions may be reset from each partition. In addition, the configuration information of the shared area between partitions may be dynamically modified.
摘要翻译：实现分区间共享存储器的分级连接的对称多处理器（SMP）已经在从每个节点的节点间连接切换的网关处，转换器用于翻译分区之间共享的区域的访问命令的地址，分区中使用的实际地址和分区之间共用的共享区域地址。由此，可以自由地设定每个分区的局部区域的地址，通过使用分层连接SMP的窥探命令，高速地进行共享区域的高速缓存一致控制。通过检查从另一个分区发出的访问命令的地址与共享区域配置之间的一致性来实现分区之间的故障保护。包括在其他分区中的节点可以从每个分区重置。此外，可以动态地修改分区之间的共享区域的配置信息。

2. 发明授权

US06546471B1 Shared memory multiprocessor performing cache coherency 失效
标题翻译：共享内存多处理器执行高速缓存一致性
公开(公告)号：US06546471B1
公开(公告)日：2003-04-08
申请号：US09506810
申请日：2000-02-18
申请人： Toshiaki Tarui , Koichi Okazawa , Yasuyuki Okada , Toru Shonai , Toshio Okochi , Hideya Akashi
发明人： Toshiaki Tarui , Koichi Okazawa , Yasuyuki Okada , Toru Shonai , Toshio Okochi , Hideya Akashi
IPC分类号： G06F1314
CPC分类号： G06F12/0826 , G06F12/0284 , G06F2212/2542
摘要： A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is “0”, a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers. The command of access to the shared area is multicast to all of the nodes, whereas the command is multicast only to the nodes within the corresponding partition when the local area is accessed.
摘要翻译：共享存储器多处理器（SMP）具有对包括在特定节点中的主存储器的有效访问以及包括节点的分区的管理。与包含在节点中的主存储器的每页对应，存储在寄存器中的位指示是否已经从任何其他节点访问了页面。在比特为“0”的情况下，不发送要发送到其他节点的高速缓存相干命令。该位在初始化和内存分配时由软件复位，当从任何其他节点访问主存储器的页面时，该位由硬件置1。在将SMP的内部划分成分区的情况下，将各节点的主存储器划分为本地区域和共享区域，分别分别分配地址。在每个节点中，共享区域和局部区域的配置信息项存储在寄存器中。访问共享区域的命令是组播到所有节点，而当访问本地区域时，该命令仅组播到相应分区内的节点。

3. 发明授权

US6088770A Shared memory multiprocessor performing cache coherency 失效
公开(公告)号：US6088770A
公开(公告)日：2000-07-11
申请号：US30957
申请日：1998-02-26
申请人： Toshiaki Tarui , Koichi Okazawa , Yasuyuki Okada , Toru Shonai , Toshio Okochi , Hideya Akashi
发明人： Toshiaki Tarui , Koichi Okazawa , Yasuyuki Okada , Toru Shonai , Toshio Okochi , Hideya Akashi
IPC分类号： G06F15/177 , G06F12/02 , G06F12/08 , G06F15/17 , G06F13/14
CPC分类号： G06F12/0826 , G06F12/0284 , G06F2212/2542
摘要： A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is "0", a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers. The command of access to the shared area is multicast to all of the nodes, whereas the command is multicast only to the nodes within the corresponding partition when the local area is accessed.

4. 发明授权

US08234584B2 Computer system, information collection support device, and method for supporting information collection 有权
标题翻译：计算机系统，信息收集支持设备和信息收集支持方法
公开(公告)号：US08234584B2
公开(公告)日：2012-07-31
申请号：US12379283
申请日：2009-02-18
申请人： Masahiro Motobayashi , Toshio Okochi , Michiko Sakai , Maki Hayashi , Akio Azuma
发明人： Masahiro Motobayashi , Toshio Okochi , Michiko Sakai , Maki Hayashi , Akio Azuma
IPC分类号： G06F3/00 , G06F17/30
CPC分类号： G06F17/30867
摘要： Provided is a computer system including an information providing server and a computer which is coupled to the information providing server, and which collects information, the computer being configured to: record status histories including a history of an operation to a screen which shows a status of the computer, and which is displayed on the computer in chronological order to constitute a set of the status histories; and divide, in a case where a history of an operation of switching the screen is detected from the set of the status histories, based on the history of the operation of switching the screen, the set of the status histories. Accordingly, when a user collects information, navigation information is provided by taking the fact that the user has actually reached useful information into consideration.
摘要翻译：提供了一种包括信息提供服务器和计算机的计算机系统，其耦合到信息提供服务器并且收集信息，该计算机被配置为：将包括操作历史的状态历史记录到显示状态计算机，并按时间顺序显示在计算机上，构成一组状态历史; 并且根据状态历史的集合，根据切换屏幕的操作的历史来检测状态历史的集合，从而从屏幕的一组中检测到切换屏幕的操作的历史的情况。因此，当用户收集信息时，通过考虑用户实际上已经考虑到有用信息的事实来提供导航信息。

5. 发明申请

US20070195949A1 Encryption processing method and encryption processing device 有权
标题翻译：加密处理方法和加密处理装置
公开(公告)号：US20070195949A1
公开(公告)日：2007-08-23
申请号：US11653879
申请日：2007-01-17
申请人： Toshio Okochi , Takashi Endo , Takashi Watanabe , Tatsuya Kameyama , Shunsuke Ota
发明人： Toshio Okochi , Takashi Endo , Takashi Watanabe , Tatsuya Kameyama , Shunsuke Ota
IPC分类号： H04L9/28
CPC分类号： H04L9/003 , G06F21/72 , G06F21/75 , G06F21/755 , H04L2209/122
摘要： An increase in safety from attacks by use of hardware-like methods by small-sized hardware is achieved. An encryption processing device includes a logical circuit capable of programmably setting logics for executing cipher processing, a memory that stores plural pieces of logical configuration information corresponding to an identical cipher processing algorithm, and a CPU that selectively sets plural logics corresponding to an identical cipher processing algorithm in the logical circuit. Even in processing using an identical cipher key, by changing the logic of the logical circuit for each processing, power consumption in cipher processing can be varied, and places a timing in which malfunctions occur can be varied. Moreover, an increase in the scale of hardware for realizing plural logics can be curbed.
摘要翻译：实现了通过使用小型硬件的类似硬件的方法的攻击来提高安全性。加密处理装置包括能够可编程地设置用于执行密码处理的逻辑的逻辑电路，存储与相同密码处理算法相对应的多条逻辑配置信息的存储器，以及选择性地设置与相同的密码处理对应的多个逻辑的CPU 算法在逻辑电路中。即使在使用相同的加密密钥的处理中，通过改变每个处理的逻辑电路的逻辑，可以改变密码处理中的功耗，并且可以改变发生故障的定时。此外，可以抑制用于实现多个逻辑的硬件规模的增加。

6. 发明授权

US08094975B2 System and method for factory work logging 有权
标题翻译：用于工厂工作记录的系统和方法
公开(公告)号：US08094975B2
公开(公告)日：2012-01-10
申请号：US12314844
申请日：2008-12-17
申请人： Toshio Okochi , Kei Suzuki , Kazuhiko Matsumoto
发明人： Toshio Okochi , Kei Suzuki , Kazuhiko Matsumoto
IPC分类号： G06K9/22
CPC分类号： G06Q10/10
摘要： Provided is an information processing system which has a plurality of tags, a tag reader, a digital-pen, and a server. The plurality of tags each hold a tag identifier. The tag reader reads the tag identifier held in each of the plurality of tags. The digital-pen reads location information, which identifies a location where handwriting is made on paper. The server keeps work record including information that associates the tag identifier recorded in the server in advance with the location on paper. When it is judged that the read tag identifier and a handwriting location identified by the location information are associated with each other, the server judges whether or not the read tag identifier matches the tag identifier recorded in advance that is associated by the work record with the handwriting location identified by the location information. The server outputs a result of the judging.
摘要翻译：提供了具有多个标签，标签读取器，数字笔和服务器的信息处理系统。多个标签各自保存标签标识符。标签读取器读取保存在多个标签中的每一个中的标签标识符。数字笔读取位置信息，其标识在纸上进行手写的位置。服务器保存工作记录，包括将服务器中记录的标签标识符与纸张上的位置预先相关联的信息。当判断出读取的标签标识符和由位置信息识别的手写位置彼此相关联时，服务器判断读取的标签标识符是否与预先记录的与工作记录相关联的标签标识符与由位置信息识别的手写位置。服务器输出判断结果。

7. 发明申请

US20090160614A1 Assembly work supporting method and system 有权
标题翻译：装配工作支持方式和制度
公开(公告)号：US20090160614A1
公开(公告)日：2009-06-25
申请号：US12314131
申请日：2008-12-04
申请人： Kazuhiko Matsumoto , Toshio Okochi , Kei Suzuki
发明人： Kazuhiko Matsumoto , Toshio Okochi , Kei Suzuki
IPC分类号： H04Q5/22
CPC分类号： G06Q50/22
摘要： Detecting whether components are combined and coupled correctly in assembly work is performed by correct and simple operations. The proposed method includes reading a first IC tag attached to a joint part of a first component and a second IC tag attached to a joint part of a second component together in a manner of preventing collision and determining whether the first component and the second component are coupled correctly, based on information representing mating relations of IC tags memorized beforehand.
摘要翻译：通过正确和简单的操作来检测组件中组件是否组合和正确耦合。所提出的方法包括以防止碰撞的方式读取附接到第一部件的接合部分的第一IC标签和附接到第二部件的接合部分的第二IC标签，并且确定第一部件和第二部件是否为基于表示事先记忆的IC标签的配对关系的信息，正确地耦合。

8. 发明申请

US20070299624A1 Method for protection of sensor node's data, a systems for secure transportation of a sensor node and a sensor node that achieves these 失效
标题翻译：用于保护传感器节点数据的方法，用于传感器节点和实现这些传感器节点的传感器节点的安全传输的系统
公开(公告)号：US20070299624A1
公开(公告)日：2007-12-27
申请号：US11806966
申请日：2007-06-05
申请人： Masahiro Motobayashi , Akiko Sato , Toshio Okochi
发明人： Masahiro Motobayashi , Akiko Sato , Toshio Okochi
IPC分类号： G01R27/28
CPC分类号： H04L63/0428 , H04L63/0869 , H04L67/12
摘要： Methods of confidential data sharing and mutual authentication between a sensor node and a router are established, and data in the sensor node is protected from a physical attack. Sensor node issuing processing is performed on a sensor node having a tamper resistant device. The sensor node issuing processing is processing in which data and a function that are deactivated are loaded in the tamper resistant device of the sensor node from the time of manufacture of the sensor node to the time the sensor node reaches a system that runs the sensor node. Activation data is used to activate the deactivated data and function. The activation data is shared between stages of the issuing processing with the use of a data management system.
摘要翻译：建立传感器节点与路由器之间机密数据共享和相互认证的方法，保护传感器节点中的数据免受物理攻击。在具有防篡改设备的传感器节点上执行传感器节点发布处理。传感器节点发布处理是从传感器节点的制造时到传感器节点到达传感器节点的系统的时刻将被去激活的数据和功能加载到传感器节点的防篡改设备中的处理。激活数据用于激活停用的数据和功能。激活数据在使用数据管理系统的发行处理的阶段之间共享。

9. 发明授权

US07206818B2 Shared memory multiprocessor system 失效
标题翻译：共享内存多处理器系统
公开(公告)号：US07206818B2
公开(公告)日：2007-04-17
申请号：US10632856
申请日：2003-08-04
申请人： Toshio Okochi , Toru Shonai , Naoki Hamanaka , Naohiko Irie , Hideya Akashi
发明人： Toshio Okochi , Toru Shonai , Naoki Hamanaka , Naohiko Irie , Hideya Akashi
IPC分类号： G06F15/167
CPC分类号： G06F15/167 , G06F2212/682
摘要： Multiprocessor system, having a translation lookaside buffer (TLB) in each processor, and having a structure for avoiding TLB purge overhead. Each processor node is provided with a partial main memory and a physical page map table (PPT). The PPT stores mapping between physical page number of main memory and virtual page number. Every memory access transaction for other node specifies physical address and virtual page number. Instead of strictly maintaining TLB coherency by broadcasting TLB purge transaction, an access destination node checks the coincidence between the virtual page number specified in the memory access transaction and the virtual page number mapped in the PPT when the transaction is received. If both are coincident, the memory access is executed. If not coincident, an error message is transferred to an access requesting source.
摘要翻译：在每个处理器中具有翻译后备缓冲器（TLB）的多处理器系统，并具有用于避免TLB清除开销的结构。每个处理器节点设置有部分主存储器和物理页映射表（PPT）。 PPT存储主存储器的物理页数和虚拟页码之间的映射。其他节点的每个内存访问事务都指定物理地址和虚拟页码。访问目的地节点不是通过广播TLB清除事务来严格维护TLB一致性，而是在接收事务时检查在存储器访问事务中指定的虚拟页号与在PPT中映射的虚拟页号之间的一致性。如果两者都一致，则执行存储器访问。如果不一致，则将错误消息传送到请求访问源。

10. 发明授权

US5752030A Program execution control in parallel processor system for parallel execution of plural jobs by selected number of processors 失效
标题翻译：并行处理器系统中的程序执行控制，用于通过选定数量的处理器并行执行多个作业
公开(公告)号：US5752030A
公开(公告)日：1998-05-12
申请号：US101993
申请日：1993-08-04
申请人： Chisato Konno , Toshio Okochi
发明人： Chisato Konno , Toshio Okochi
IPC分类号： G06F9/45 , G06F9/50 , G06F15/16 , G06F15/177 , G06F9/40
CPC分类号： G06F9/5027 , G06F9/4881 , G06F2209/5014
摘要： In submitting each job in a parallel processing system provided with a plurality of processors, execution conditions such as a requested minimum processor number, an upper limit used processor number and a requested execution time are designated for each job and the judgement of whether or not processors equal in number to the requested minimum processor number required by a leading one of execution waiting jobs are in idle states is made for the leading job by use of a table for managing the status of utilization of processors for each job executed and the number of idle processors, a table for managing processors occupied or used by each operating job and a lapse time and a table for managing the execution conditions of each execution waiting job. When idle processors to be assigned are lacking, information in the above tables is used to judge whether a wait until processors corresponding to a number required by that job become idle states is taken without activating a subsequent job or the subsequent job should be activated ahead.
摘要翻译：在提供有多个处理器的并行处理系统中提交每个作业时，为每个作业指定执行条件，例如所请求的最小处理器号，上限使用的处理器号和请求的执行时间，并判断处理器通过使用用于管理执行的每个作业的处理器的使用状态和空闲数量的表来为领先作业做出与执行等待作业的前一个处于空闲状态所要求的最小处理器数量相等的数量处理器，用于管理每个操作作业占用或使用的处理器的表以及经过时间以及用于管理每个执行等待作业的执行条件的表。当缺少要分配的空闲处理器时，使用上表中的信息来判断是否等待直到与该作业所需的号码相对应的处理器变为空闲状态，而不激活后续作业，或者应该在后面激活后续作业。

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