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1. 发明授权

US06444514B1 Semiconductor integrated circuit device and manufacturing method thereof 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06444514B1
公开(公告)日：2002-09-03
申请号：US09677758
申请日：2000-10-03
申请人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
发明人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0483 , H01L21/76229 , H01L21/823412 , H01L21/823481 , H01L27/115
摘要： In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.
摘要翻译：在半导体集成电路装置中，在形成有条状元件分离区域5的基板上形成有AND型闪速存储器，并且夹持在元件分离区域5之间的有源区域L形成为条状。使用含有氮或碳的硅单晶衬底作为半导体衬底，以减少错位缺陷和结漏电，从而提高可靠性和产率。

2. 发明授权

US06815761B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06815761B2
公开(公告)日：2004-11-09
申请号：US10419944
申请日：2003-04-22
申请人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
发明人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0483 , H01L21/76229 , H01L21/823412 , H01L21/823481 , H01L27/115
摘要： In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.

3. 发明授权

US06583467B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06583467B2
公开(公告)日：2003-06-24
申请号：US10179217
申请日：2002-06-26
申请人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
发明人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0483 , H01L21/76229 , H01L21/823412 , H01L21/823481 , H01L27/115
摘要： In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.
摘要翻译：在半导体集成电路装置中，在形成有条状元件分离区域5的基板上形成有AND型闪速存储器，并且夹持在元件分离区域5之间的有源区域L形成为条状。使用含有氮或碳的硅单晶衬底作为半导体衬底，以减少错位缺陷和接头泄漏，从而提高可靠性和产率。

4. 发明授权

US6043114A Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device 失效
公开(公告)号：US6043114A
公开(公告)日：2000-03-28
申请号：US934774
申请日：1997-09-22
申请人： Hiroto Kawagoe , Tatsumi Shirasu , Shogo Kiyota , Norio Suzuki , Eiichi Yamada , Yuji Sugino , Manabu Kitano , Yoshihiko Sakurai , Takashi Naganuma , Hisashi Arakawa
发明人： Hiroto Kawagoe , Tatsumi Shirasu , Shogo Kiyota , Norio Suzuki , Eiichi Yamada , Yuji Sugino , Manabu Kitano , Yoshihiko Sakurai , Takashi Naganuma , Hisashi Arakawa
IPC分类号： H01L29/78 , H01L21/205 , H01L21/8238 , H01L27/092 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/0925 , H01L21/823807
摘要： Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.

5. 发明授权

US06630375B2 Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device 有权
公开(公告)号：US06630375B2
公开(公告)日：2003-10-07
申请号：US10002147
申请日：2001-12-05
申请人： Hiroto Kawagoe , Tatsumi Shirasu , Shogo Kiyota , Norio Suzuki , Eiichi Yamada , Yuji Sugino , Manabu Kitano , Yoshihiko Sakurai , Takashi Naganuma , Hisashi Arakawa
发明人： Hiroto Kawagoe , Tatsumi Shirasu , Shogo Kiyota , Norio Suzuki , Eiichi Yamada , Yuji Sugino , Manabu Kitano , Yoshihiko Sakurai , Takashi Naganuma , Hisashi Arakawa
IPC分类号： H01L218238
CPC分类号： H01L27/0925 , H01L21/823807
摘要： Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS·FETs.

6. 发明授权

US06368905B1 Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device 有权
标题翻译：用于制造半导体晶片的工艺，半导体晶片，半导体集成电路器件的制造工艺以及半导体集成电路器件
公开(公告)号：US06368905B1
公开(公告)日：2002-04-09
申请号：US09513349
申请日：2000-02-25
申请人： Hiroto Kawagoe , Tatsumi Shirasu , Shogo Kiyota , Norio Suzuki , Eiichi Yamada , Yuji Sugino , Manabu Kitano , Yoshihiko Sakurai , Takashi Naganuma , Hisashi Arakawa
发明人： Hiroto Kawagoe , Tatsumi Shirasu , Shogo Kiyota , Norio Suzuki , Eiichi Yamada , Yuji Sugino , Manabu Kitano , Yoshihiko Sakurai , Takashi Naganuma , Hisashi Arakawa
IPC分类号： H01L218238
CPC分类号： H01L27/0925 , H01L21/823807
摘要： Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.
摘要翻译：在包含预定导电类型的杂质的半导体衬底主体的主表面上，形成外延层，该外延层含有与前一种杂质相同的导电类型的杂质，并且与前者中设计的杂质相同不纯。之后，形成具有与所述杂质相同的导电类型的阱区，并且其杂质浓度从所述外延层的深度逐渐降低。阱区由MIS.FET的栅极绝缘膜形成。

7. 发明授权

US07005673B2 ITO film-formed substrate, and manufacturing method thereof 失效
标题翻译： ITO膜形成基板及其制造方法
公开(公告)号：US07005673B2
公开(公告)日：2006-02-28
申请号：US10754249
申请日：2004-01-09
申请人： Shogo Kiyota , Yukihiro Katoh
发明人： Shogo Kiyota , Yukihiro Katoh
IPC分类号： H01L35/24
CPC分类号： G02F1/13439 , G02F1/133514 , G02F2001/133519
摘要： An ITO film-formed substrate having excellent alkali resistance and adhesion is provided. For the ITO film-formed substrate, a structure is adopted in which a color filter 102, an organic protective film 103, intermediate layers 104a and 104b, and an ITO film 105 having an electrode pattern patterned therein are formed in this order from the bottom upwards on a surface of a glass substrate 101. The intermediate layer 104a is deposited on a surface of the organic protective film 103 through a high-frequency sputtering method using Ar as an introduced gas, and is made of a metal oxide that is not prone to dissolving in alkalis; the intermediate layer 104b is deposited through a reactive sputtering method or a high-frequency sputtering method, and is made of a metal oxide or metal nitride that is not prone to dissolving in alkalis.
摘要翻译：提供了具有优异的耐碱性和粘附性的ITO膜形成基材。对于ITO膜形成的基板，采用以下结构，其中以其顺序形成滤色器102，有机保护膜103，中间层104a和104b以及其中形成图案的电极图案的ITO膜105 在玻璃基板101的表面上向下的底部。中间层104a通过使用Ar作为引入气体的高频溅射法沉积在有机保护膜103的表面上，并且由不容易溶解在碱中的金属氧化物制成; 中间层104b通过反应溅射法或高频溅射法沉积，并且由不容易溶解在碱中的金属氧化物或金属氮化物制成。

8. 发明授权

US06685805B2 Method of manufacturing substrate having transparent conductive film, substrate having transparent conductive film manufactured using the method, and touch panel using the substrate 有权
标题翻译：制造具有透明导电膜的基板的方法，使用该方法制造的具有透明导电膜的基板和使用该基板的触摸面板
公开(公告)号：US06685805B2
公开(公告)日：2004-02-03
申请号：US09909570
申请日：2001-07-20
申请人： Shogo Kiyota , Yukihiro Katoh
发明人： Shogo Kiyota , Yukihiro Katoh
IPC分类号： C23C1434
CPC分类号： G06F3/045 , C23C14/086 , H01B1/08 , H01H13/785 , H01H2201/028 , H01H2209/084
摘要： In a method of manufacturing a substrate having a transparent conductive film in which sputtering is carried out on a transparent insulating substrate using an indium oxide/tin oxide target under an atmosphere of a mixed gas containing argon and oxygen, when the ratio of oxygen to argon in the mixed gas is in a suitable range of 0.016 to 0.018, the carrier density of the transparent conductive film becomes a maximum, while the mobility rises progressively as the ratio of oxygen to argon increases. The surface resistance of the transparent conductive film, that is the reciprocal of the product of the carrier density and the mobility, 1/(carrier density×mobility), takes a minimum value when the ratio of oxygen to argon is in the above suitable range. In this case, crystallization of the film is promoted and the percentage change between the surface resistance of the film before heat treatment and the surface resistance of the film after heat treatment can be kept down to within ±10%.
摘要翻译：在制造具有透明导电膜的基板的方法中，其中在含有氩和氧的混合气体的气氛下，在使用氧化铟/氧化锡靶的透明绝缘基板上进行溅射，当氧与氩的比例在混合气体的合适范围为0.016〜0.018的范围内，透明导电膜的载流子密度变得最大，而随着氧与氩的比例增加，迁移率逐渐上升。当氧与氩的比例在上述适当范围内时，透明导电膜的表面电阻，即载流子密度乘积和迁移率1 /（载流子密度迁移率）的乘积的倒数为最小值。在这种情况下，促进了膜的结晶，并且热处理前的膜的表面电阻与热处理后的膜的表面电阻之间的百分比变化可以保持在±10％以内。

9. 发明授权

US06806130B2 Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device 失效
标题翻译：用于制造半导体晶片的工艺，半导体晶片，半导体集成电路器件的制造工艺以及半导体集成电路器件
公开(公告)号：US06806130B2
公开(公告)日：2004-10-19
申请号：US10014405
申请日：2001-12-14
申请人： Hiroto Kawagoe , Tatsumi Shirasu , Shogo Kiyota , Norio Suzuki , Eiichi Yamada , Yuji Sugino , Manabu Kitano , Yoshihiko Sakurai , Takashi Naganuma , Hisashi Arakawa
发明人： Hiroto Kawagoe , Tatsumi Shirasu , Shogo Kiyota , Norio Suzuki , Eiichi Yamada , Yuji Sugino , Manabu Kitano , Yoshihiko Sakurai , Takashi Naganuma , Hisashi Arakawa
IPC分类号： H01L218238
CPC分类号： H01L27/0925 , H01L21/823807
摘要： Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS·FETs.
摘要翻译：在包含预定导电类型的杂质的半导体衬底主体的主表面上，形成外延层，该外延层含有与前一种杂质相同的导电类型的杂质，并且与前者中设计的杂质相同不纯。之后，形成具有与所述杂质相同的导电类型的阱区，并且其杂质浓度从所述外延层的深度逐渐降低。阱区由MIS.FET的栅极绝缘膜形成。

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