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1. 发明授权

US07528078B2 Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer 有权
标题翻译：形成电子器件的工艺包括与半导体层内的开口相邻的致密的氮化物层
公开(公告)号：US07528078B2
公开(公告)日：2009-05-05
申请号：US11433298
申请日：2006-05-12
申请人： Toni D. Van Gompel , Kuang-Hsin Chen , Laegu Kang , Rode R. Mora , Michael D. Turner
发明人： Toni D. Van Gompel , Kuang-Hsin Chen , Laegu Kang , Rode R. Mora , Michael D. Turner
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31111 , H01L21/3105 , H01L21/31116 , H01L21/76205
摘要： A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include depositing a nitride layer within the opening, wherein depositing is performed using a PECVD technique. The process can further include densifying the nitride layer. The process can still further include removing a part of the nitride layer, wherein a remaining portion of the nitride layer can lie within the opening and be spaced apart from the surface.
摘要翻译：形成电子器件的过程可以包括图案化半导体层以限定延伸到绝缘层的开口，其中绝缘层位于衬底和半导体层之间。在图案化半导体层之后，开口可以具有底部，并且半导体层可以具有侧壁和表面。表面可以与绝缘层间隔开，并且侧壁可以从表面延伸到绝缘层。该方法还可以包括在开口内沉积氮化物层，其中使用PECVD技术进行沉积。该方法还可以包括使氮化物层致密化。该方法还可以进一步包括去除氮化物层的一部分，其中氮化物层的剩余部分可以位于开口内并且与表面间隔开。

2. 发明授权

US07265425B2 Semiconductor device employing an extension spacer and a method of forming the same 有权
标题翻译：采用延伸间隔物的半导体装置及其形成方法
公开(公告)号：US07265425B2
公开(公告)日：2007-09-04
申请号：US10989073
申请日：2004-11-15
申请人： Kuang-Hsin Chen , Tang-Xuan Zhong , Chien-Chao Huang , Cheng-Kuo Wen , Di-Hong Lee
发明人： Kuang-Hsin Chen , Tang-Xuan Zhong , Chien-Chao Huang , Cheng-Kuo Wen , Di-Hong Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/76829 , H01L29/51 , H01L29/6656 , H01L29/66575 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.
摘要翻译：形成在半导体衬底上的半导体器件及其形成方法。在一个实施例中，半导体器件包括半导体衬底上的栅极和栅极侧壁上的电介质衬垫。该半导体器件还包括一个与半导体衬底相邻且沿着绝缘衬垫横向延伸延伸的间隔件。半导体器件还包括位于半导体衬底的上表面下方并与栅极下方的沟道区相邻的源极/漏极。源极/漏极延伸在电介质衬垫和延伸垫片下面。半导体器件还包括在源极/漏极的一部分上方的硅化物区域，并且沿着半导体衬底横向延伸超过延伸间隔物。因此，延伸间隔物介于电介质衬垫和位于源极/漏极的一部分之上的硅化物区域之间。

3. 发明申请

US20060202237A1 Metal gate semiconductor device and manufacturing method 有权
标题翻译：金属栅极半导体器件及其制造方法
公开(公告)号：US20060202237A1
公开(公告)日：2006-09-14
申请号：US11400853
申请日：2006-04-10
申请人： Chien-Chao Huang , Kuang-Hsin Chen , Fu-Liang Yang
发明人： Chien-Chao Huang , Kuang-Hsin Chen , Fu-Liang Yang
IPC分类号： H01L29/768
CPC分类号： H01L29/66553 , H01L21/28097 , H01L21/82345 , H01L21/823468 , H01L29/665 , H01L29/66507 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.
摘要翻译：一种用于制造金属栅极的方法包括提供包括位于基板上的栅电极的基板。形成多个层，包括位于衬底上的第一层和栅电极以及与第一层相邻的第二层。这些层被蚀刻以形成多个相邻的间隔物，包括位于衬底上并且邻近栅电极的第一间隔物和邻近第一间隔物的第二间隔物。然后蚀刻第一间隔物，并且在紧邻栅电极的器件上形成金属层。然后金属层与栅电极反应形成金属栅极。

4. 发明申请

US20070272954A1 FIN-FET device structure formed employing bulk semiconductor substrate 有权
标题翻译：使用体半导体衬底形成的FIN-FET器件结构
公开(公告)号：US20070272954A1
公开(公告)日：2007-11-29
申请号：US11441724
申请日：2006-05-27
申请人： Kuang-Hsin Chen , Hsun-Chih Tsao , Jhi-Cherng Lu , Chuan-Ping Hou , Peng-Fu Hsu , Hung-Wei Chen , Di-Hong Lee
发明人： Kuang-Hsin Chen , Hsun-Chih Tsao , Jhi-Cherng Lu , Chuan-Ping Hou , Peng-Fu Hsu , Hung-Wei Chen , Di-Hong Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.
摘要翻译：翅片FET器件及其制造方法都采用体半导体衬底。在体半导体衬底内形成翅片和相邻的槽。槽部分地用沉积的介电层回填以形成暴露的翅片区域和未曝光的翅片区域。在暴露的散热片区域上形成栅极电介质层，在栅极电介质层上形成栅电极。通过采用体半导体衬底，成本有效地制造了鳍式FET器件。

5. 发明申请

US20060289920A1 COMPOSITE GATE STRUCTURE IN AN INTEGRATED CIRCUIT 有权
标题翻译：集成电路中的复合门结构
公开(公告)号：US20060289920A1
公开(公告)日：2006-12-28
申请号：US11158764
申请日：2005-06-22
申请人： I-Lu Wu , Kuang-Hsin Chen , Liang-Kai Han
发明人： I-Lu Wu , Kuang-Hsin Chen , Liang-Kai Han
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L21/823842 , H01L21/823857 , H01L29/785
摘要： An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.
摘要翻译：提供一种具有复合栅结构的集成电路及其形成方法。集成电路包括第一MOS器件，第二MOS器件和第三MOS器件。第一MOS器件的栅极堆叠包括高k栅极电介质和高k栅极电介质上的第一金属栅极。第二MOS器件的栅极堆叠包括在高k栅极电介质上的第二金属栅极。第一金属门和第二金属门具有不同的功能。第三MOS器件的栅极堆叠包括栅极电介质上的硅栅极。硅栅极优选形成在第一MOS器件和第二MOS器件的栅极堆叠之上。

6. 发明申请

US20060102955A1 Semiconductor device employing an extension spacer and a method of forming the same 有权
标题翻译：采用延伸间隔物的半导体装置及其形成方法
公开(公告)号：US20060102955A1
公开(公告)日：2006-05-18
申请号：US10989073
申请日：2004-11-15
申请人： Kuang-Hsin Chen , Tang-Xuan Zhong , Chien-Chao Huang , Cheng-Kuo Wen , Di-Hong Lee
发明人： Kuang-Hsin Chen , Tang-Xuan Zhong , Chien-Chao Huang , Cheng-Kuo Wen , Di-Hong Lee
IPC分类号： H01L21/338 , H01L31/062
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/76829 , H01L29/51 , H01L29/6656 , H01L29/66575 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.
摘要翻译：形成在半导体衬底上的半导体器件及其形成方法。在一个实施例中，半导体器件包括半导体衬底上的栅极和栅极侧壁上的电介质衬垫。该半导体器件还包括一个与半导体衬底相邻且沿着绝缘衬垫横向延伸延伸的间隔件。半导体器件还包括位于半导体衬底的上表面下方并与栅极下方的沟道区相邻的源极/漏极。源极/漏极延伸在电介质衬垫和延伸垫片下面。半导体器件还包括在源极/漏极的一部分上方的硅化物区域，并且沿着半导体衬底横向延伸超过延伸间隔物。因此，延伸间隔物介于电介质衬垫和位于源极/漏极的一部分之上的硅化物区域之间。

7. 发明申请

US20050145937A1 STI liner for SOI structure 有权
公开(公告)号：US20050145937A1
公开(公告)日：2005-07-07
申请号：US10747494
申请日：2003-12-29
申请人： Kuang-Hsin Chen , Hsun-Chih Tsao , Hung-Wei Chen , Di-Hong Lee , Chuan-Ping Hou , Jhi-Cherng Lu
发明人： Kuang-Hsin Chen , Hsun-Chih Tsao , Hung-Wei Chen , Di-Hong Lee , Chuan-Ping Hou , Jhi-Cherng Lu
IPC分类号： H01L21/00 , H01L21/20 , H01L21/762 , H01L21/84 , H01L27/01
CPC分类号： H01L21/76224 , H01L21/84
摘要： In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.

8. 发明授权

US07923759B2 Metal gate semiconductor device and manufacturing method 有权
标题翻译：金属栅极半导体器件及其制造方法
公开(公告)号：US07923759B2
公开(公告)日：2011-04-12
申请号：US11400853
申请日：2006-04-10
申请人： Chien-Chao Huang , Kuang-Hsin Chen , Fu-Liang Yang
发明人： Chien-Chao Huang , Kuang-Hsin Chen , Fu-Liang Yang
IPC分类号： H01L29/768
CPC分类号： H01L29/66553 , H01L21/28097 , H01L21/82345 , H01L21/823468 , H01L29/665 , H01L29/66507 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.
摘要翻译：一种用于制造金属栅极的方法包括提供包括位于基板上的栅电极的基板。形成多个层，包括位于衬底上的第一层和栅电极以及与第一层相邻的第二层。这些层被蚀刻以形成多个相邻的间隔物，包括位于衬底上并且邻近栅电极的第一间隔物和邻近第一间隔物的第二间隔物。然后蚀刻第一间隔物，并且在紧邻栅电极的器件上形成金属层。然后金属层与栅电极反应形成金属栅极。

9. 发明授权

US07663185B2 FIN-FET device structure formed employing bulk semiconductor substrate 有权
标题翻译：使用体半导体衬底形成的FIN-FET器件结构
公开(公告)号：US07663185B2
公开(公告)日：2010-02-16
申请号：US11441724
申请日：2006-05-27
申请人： Kuang-Hsin Chen , Hsun-Chih Tsao , Jhi-Cherng Lu , Chuan-Ping Hou , Peng-Fu Hsu , Hung-Wei Chen , Di-Hong Lee
发明人： Kuang-Hsin Chen , Hsun-Chih Tsao , Jhi-Cherng Lu , Chuan-Ping Hou , Peng-Fu Hsu , Hung-Wei Chen , Di-Hong Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.
摘要翻译：翅片FET器件及其制造方法都采用体半导体衬底。在体半导体衬底内形成翅片和相邻的槽。槽部分地用沉积的介电层回填以形成暴露的翅片区域和未曝光的翅片区域。在暴露的散热片区域上形成栅极电介质层，在栅极电介质层上形成栅电极。通过采用体半导体衬底，成本有效地制造了鳍式FET器件。

10. 发明授权

US07332777B2 STI liner for SOI structure 有权
标题翻译： STI衬垫为SOI结构
公开(公告)号：US07332777B2
公开(公告)日：2008-02-19
申请号：US11221200
申请日：2005-09-07
申请人： Kuang-Hsin Chen , Hsun-Chih Tsao , Hung-Wei Chen , Di-Hong Lee , Chuan-Ping Hou , Jhi-Cherng Lu
发明人： Kuang-Hsin Chen , Hsun-Chih Tsao , Hung-Wei Chen , Di-Hong Lee , Chuan-Ping Hou , Jhi-Cherng Lu
IPC分类号： H01L31/0392
CPC分类号： H01L21/76224 , H01L21/84
摘要： In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.
摘要翻译：在制造半导体器件的方法中，提供了初始结构。初始结构包括衬底，图案化硅层和覆盖层。基板上形成有埋置的绝缘体层。图案化的硅层形成在掩埋绝缘体层上。覆盖层形成在图案化硅层上。在初始结构上形成第一层。通过蚀刻工艺去除第一层的一部分，使得图案化硅层的侧壁部分被暴露，并且使得第一层的剩余部分保留在图案化硅层与掩埋绝缘体层接合的拐角处。在暴露的侧壁部分上形成氧化物衬垫。可以在掩埋绝缘体层（在形成第一层之前）形成凹部，并且可以在图案化的硅层的部分下方延伸。

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